diff --git a/litedram/gen.py b/litedram/gen.py
index 82cef59..ba50e7f 100644
--- a/litedram/gen.py
+++ b/litedram/gen.py
@@ -258,12 +258,14 @@ class LiteDRAMCore(SoCSDRAM):
             kwargs["integrated_rom_size"]  = 0
             kwargs["integrated_sram_size"] = 0
             kwargs["l2_size"]              = 0
+            kwargs["l2_data_width"]        = 32
             kwargs["with_uart"]            = False
             kwargs["with_timer"]           = False
             kwargs["with_ctrl"]            = False
             kwargs["with_wishbone"]        = (cpu_type != None)
         else:
-           kwargs["l2_size"] = 0
+           kwargs["l2_size"]       = 0
+           kwargs["l2_data_width"] = 32
 
         # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, sys_clk_freq,