From c07f4a1f1bc5a0916e8107902574de7c6ede0fbc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Jan 2020 17:31:17 +0100 Subject: [PATCH] gen: add l2_data_width to kwargs --- litedram/gen.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/litedram/gen.py b/litedram/gen.py index 82cef59..ba50e7f 100644 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -258,12 +258,14 @@ class LiteDRAMCore(SoCSDRAM): kwargs["integrated_rom_size"] = 0 kwargs["integrated_sram_size"] = 0 kwargs["l2_size"] = 0 + kwargs["l2_data_width"] = 32 kwargs["with_uart"] = False kwargs["with_timer"] = False kwargs["with_ctrl"] = False kwargs["with_wishbone"] = (cpu_type != None) else: - kwargs["l2_size"] = 0 + kwargs["l2_size"] = 0 + kwargs["l2_data_width"] = 32 # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, sys_clk_freq,