From b4a2b7f9b06882e79ad4d13cff65cab42596ea5e Mon Sep 17 00:00:00 2001 From: Andrew Butt Date: Tue, 27 Apr 2021 02:08:31 -0400 Subject: [PATCH] Fix UpConverter reversed write mask Signed-off-by: Andrew Butt --- litedram/frontend/adapter.py | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/litedram/frontend/adapter.py b/litedram/frontend/adapter.py index 9bab787..1a887c0 100644 --- a/litedram/frontend/adapter.py +++ b/litedram/frontend/adapter.py @@ -309,10 +309,17 @@ class LiteDRAMNativePortUpConverter(Module): # Replicate `sel` bits to match the width of port_to.wdata.we. wdata_sel = Signal.like(port_to.wdata.we) - wdata_sel_parts = [ - Replicate(cmd_buffer.source.sel[i], port_to.wdata.we.nbits // sel.nbits) - for i in range(ratio) - ] + if reverse: + wdata_sel_parts = [ + Replicate(cmd_buffer.source.sel[i], port_to.wdata.we.nbits // sel.nbits) + for i in reverse(range(ratio)) + ] + else: + wdata_sel_parts = [ + Replicate(cmd_buffer.source.sel[i], port_to.wdata.we.nbits // sel.nbits) + for i in range(ratio) + ] + self.sync += \ If(cmd_buffer.source.valid & cmd_buffer.source.we & wdata_chunk[ratio - 1], wdata_sel.eq(Cat(wdata_sel_parts))