From 6595567fa8eefb8850eab91f53e5482c31c714cd Mon Sep 17 00:00:00 2001 From: Mariusz Glebocki Date: Wed, 5 Feb 2020 15:38:40 +0100 Subject: [PATCH] modules: MT18KSF1G72HZ: use float as tWR value Fixes error: $ litex_sim --with-sdram --sdram-module MT18KSF1G72HZ Traceback (most recent call last): File "bin/litex_sim", line 11, in load_entry_point('litex', 'console_scripts', 'litex_sim')() File "litex/litex/tools/litex_sim.py", line 301, in main **soc_kwargs) File "litex/litex/tools/litex_sim.py", line 187, in __init__ sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate) File "litedram/litedram/modules.py", line 65, in __init__ File "litedram/litedram/modules.py", line 110, in ns_to_cycles TypeError: can only concatenate tuple (not "float") to tuple --- litedram/modules.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/modules.py b/litedram/modules.py index 60b6ed2..ddd2073 100644 --- a/litedram/modules.py +++ b/litedram/modules.py @@ -467,7 +467,7 @@ class MT18KSF1G72HZ(SDRAMModule): speedgrade_timings = { "1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(86, None), tFAW=(None, 50), tRAS=None), "1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(107, None), tFAW=(None, 45), tRAS=None), - "1600": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=(13.125, None), tRFC=(128, None), tFAW=(None, 40), tRAS=None), + "1600": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=13.125, tRFC=(128, None), tFAW=(None, 40), tRAS=None), } speedgrade_timings["default"] = speedgrade_timings["1600"]