From c29c898af4d41571f694ca2fc38ce7d6137d26f6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 4 Jan 2021 14:11:32 +0100 Subject: [PATCH] platforms/targets: switch to LiteX-Boards. --- bench/genesys2.py | 2 +- bench/kc705.py | 2 +- bench/kcu105.py | 2 +- test/test_init.py | 6 +++--- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/bench/genesys2.py b/bench/genesys2.py index 171e7de..a617cea 100755 --- a/bench/genesys2.py +++ b/bench/genesys2.py @@ -11,7 +11,7 @@ import argparse from migen import * -from litex.boards.platforms import genesys2 +from litex_boards.platforms import genesys2 from litex.soc.cores.clock import * from litex.soc.interconnect.csr import * diff --git a/bench/kc705.py b/bench/kc705.py index 57ac72a..4dcd908 100755 --- a/bench/kc705.py +++ b/bench/kc705.py @@ -11,7 +11,7 @@ import argparse from migen import * -from litex.boards.platforms import kc705 +from litex_boards.platforms import kc705 from litex.soc.cores.clock import * from litex.soc.interconnect.csr import * diff --git a/bench/kcu105.py b/bench/kcu105.py index f5669fb..020f6c5 100755 --- a/bench/kcu105.py +++ b/bench/kcu105.py @@ -12,7 +12,7 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex.boards.platforms import kcu105 +from litex_boards.platforms import kcu105 from litex.soc.cores.clock import * from litex.soc.interconnect.csr import * diff --git a/test/test_init.py b/test/test_init.py index 8c9e45d..9d1ee84 100644 --- a/test/test_init.py +++ b/test/test_init.py @@ -22,7 +22,7 @@ def compare_with_reference(content, filename): class TestInit(unittest.TestCase): def test_sdr(self): - from litex.boards.targets.minispartan6 import BaseSoC + from litex_boards.targets.minispartan6 import BaseSoC soc = BaseSoC() c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) @@ -30,7 +30,7 @@ class TestInit(unittest.TestCase): self.assertEqual(compare_with_reference(py_header, "sdr_init.py"), True) def test_ddr3(self): - from litex.boards.targets.kc705 import BaseSoC + from litex_boards.targets.kc705 import BaseSoC soc = BaseSoC() c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) @@ -38,7 +38,7 @@ class TestInit(unittest.TestCase): self.assertEqual(compare_with_reference(py_header, "ddr3_init.py"), True) def test_ddr4(self): - from litex.boards.targets.kcu105 import BaseSoC + from litex_boards.targets.kcu105 import BaseSoC soc = BaseSoC(max_sdram_size=0x4000000) c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing) py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)