From c2a779df4658d599488e5137858cd95b201538ba Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 19 Apr 2021 13:40:17 +0200 Subject: [PATCH] bench: Update test targets (add_csr no longer required). --- bench/arty.py | 5 ----- bench/genesys2.py | 5 ----- bench/kc705.py | 5 ----- bench/kcu105.py | 5 ----- bench/xcu1525.py | 4 ---- 5 files changed, 24 deletions(-) diff --git a/bench/arty.py b/bench/arty.py index e44bbc1..07f9d00 100755 --- a/bench/arty.py +++ b/bench/arty.py @@ -77,14 +77,12 @@ class BenchSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) - self.add_csr("crg") # DDR3 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41K128M16(sys_clk_freq, "1:4"), @@ -100,7 +98,6 @@ class BenchSoC(SoCCore): clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), with_hw_init_reset = False) - self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy) # Analyzer --------------------------------------------------------------------------------- @@ -111,14 +108,12 @@ class BenchSoC(SoCCore): depth = 256, clock_domain = "sys", csr_csv = "analyzer.csv") - self.add_csr("analyzer") # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Main --------------------------------------------------------------------------------------------- diff --git a/bench/genesys2.py b/bench/genesys2.py index db79364..e8dd14f 100755 --- a/bench/genesys2.py +++ b/bench/genesys2.py @@ -71,14 +71,12 @@ class BenchSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) - self.add_csr("crg") # DDR3 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT41J256M16(sys_clk_freq, "1:4"), @@ -94,7 +92,6 @@ class BenchSoC(SoCCore): clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), with_hw_init_reset = False) - self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy) # Analyzer --------------------------------------------------------------------------------- @@ -105,14 +102,12 @@ class BenchSoC(SoCCore): depth = 512, clock_domain = "sys", csr_csv = "analyzer.csv") - self.add_csr("analyzer") # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Main --------------------------------------------------------------------------------------------- diff --git a/bench/kc705.py b/bench/kc705.py index e465b9e..8b6f281 100755 --- a/bench/kc705.py +++ b/bench/kc705.py @@ -71,14 +71,12 @@ class BenchSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) - self.add_csr("crg") # DDR3 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT8JTF12864(sys_clk_freq, "1:4"), @@ -94,7 +92,6 @@ class BenchSoC(SoCCore): clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), clk_freq = self.clk_freq) - self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy) # Analyzer --------------------------------------------------------------------------------- @@ -105,14 +102,12 @@ class BenchSoC(SoCCore): depth = 256, clock_domain = "sys", csr_csv = "analyzer.csv") - self.add_csr("analyzer") # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Main --------------------------------------------------------------------------------------------- diff --git a/bench/kcu105.py b/bench/kcu105.py index 5902518..71af9f5 100755 --- a/bench/kcu105.py +++ b/bench/kcu105.py @@ -89,14 +89,12 @@ class BenchSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) - self.add_csr("crg") # DDR4 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), memtype = "DDR4", sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = EDY4016A(sys_clk_freq, "1:4"), @@ -112,7 +110,6 @@ class BenchSoC(SoCCore): self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk, data_pads = self.platform.request("sfp", 0), sys_clk_freq = self.clk_freq) - self.add_csr("ethphy") self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1) self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]") self.add_etherbone(phy=self.ethphy) @@ -125,14 +122,12 @@ class BenchSoC(SoCCore): depth = 256, clock_domain = "sys", csr_csv = "analyzer.csv") - self.add_csr("analyzer") # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Main --------------------------------------------------------------------------------------------- diff --git a/bench/xcu1525.py b/bench/xcu1525.py index f8d6598..f7d616e 100755 --- a/bench/xcu1525.py +++ b/bench/xcu1525.py @@ -85,14 +85,12 @@ class BenchSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, channel) - self.add_csr("crg") # DDR4 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram", channel), memtype = "DDR4", sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6) - self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, module = MT40A512M8(sys_clk_freq, "1:4"), @@ -114,14 +112,12 @@ class BenchSoC(SoCCore): depth = 256, clock_domain = "sys", csr_csv = "analyzer.csv") - self.add_csr("analyzer") # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) - self.add_csr("leds") # Main ---------------------------------------------------------------------------------------------