From c30910a9d29954e14494aaf6560424e87a1ba89e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 18 May 2020 23:06:33 +0200 Subject: [PATCH] init: generate DFII_CONTROL flags in sdram_phy.h instead of defining them in the BIOS. --- litedram/init.py | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/litedram/init.py b/litedram/init.py index 2620790..6f5c034 100644 --- a/litedram/init.py +++ b/litedram/init.py @@ -448,7 +448,20 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings): def get_sdram_phy_c_header(phy_settings, timing_settings): r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n" - r += "#include \n#include \n#include \n\n" + r += "#include \n" + r += "#include \n" + + r += "#define DFII_CONTROL_SEL 0x01\n" + r += "#define DFII_CONTROL_CKE 0x02\n" + r += "#define DFII_CONTROL_ODT 0x04\n" + r += "#define DFII_CONTROL_RESET_N 0x08\n" + + r += "#define DFII_COMMAND_CS 0x01\n" + r += "#define DFII_COMMAND_WE 0x02\n" + r += "#define DFII_COMMAND_CAS 0x04\n" + r += "#define DFII_COMMAND_RAS 0x08\n" + r += "#define DFII_COMMAND_WRDATA 0x10\n" + r += "#define DFII_COMMAND_RDDATA 0x20\n" phytype = phy_settings.phytype.upper() nphases = phy_settings.nphases