From c3963a18879483fc834ab535c2c907718ab5ce3f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 1 Jun 2023 08:45:47 +0200 Subject: [PATCH] frontend/avalon: Decouple Cmd and Data-paths in BURST-WRITE (We don't need to wait that wdata_fifo is empty to return to Idle). --- litedram/frontend/avalon.py | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/litedram/frontend/avalon.py b/litedram/frontend/avalon.py index e6440f4..2edd081 100644 --- a/litedram/frontend/avalon.py +++ b/litedram/frontend/avalon.py @@ -104,9 +104,9 @@ class LiteDRAMAvalonMM2Native(LiteXModule): ).Else( port.cmd.addr.eq(avalon.address - address_offset), port.cmd.we.eq(avalon.write), - port.cmd.valid.eq(1), + port.cmd.valid.eq(avalon.read | (avalon.write & wdata_fifo.sink.ready)), port.cmd.last.eq(1), - If(port.cmd.ready, + If(port.cmd.valid & port.cmd.ready, avalon.waitrequest.eq(0), If(port.cmd.we, NextState("SINGLE-WRITE") @@ -137,21 +137,16 @@ class LiteDRAMAvalonMM2Native(LiteXModule): port.cmd.addr.eq(address), port.cmd.we.eq(1), port.cmd.valid.eq(avalon.write & wdata_fifo.sink.ready), + port.cmd.last.eq(burst_count == 1), If(port.cmd.valid & port.cmd.ready, - avalon.waitrequest.eq(0) - ), - If(burst_count > 0, - If(port.cmd.valid & port.cmd.ready, + avalon.waitrequest.eq(0), + If(port.cmd.last, + NextState("IDLE") + ).Else( NextValue(burst_count, burst_count - 1), NextValue(address, address + burst_increment) ) - ).Else( - avalon.waitrequest.eq(1), - # Wait for the FIFO to be empty - If((~port.cmd.valid) & (~wdata_fifo.source.valid), - NextState("IDLE") - ) - ), + ) ) fsm.act("BURST-READ",