diff --git a/litedram/init.py b/litedram/init.py
index f224de0..597dea5 100644
--- a/litedram/init.py
+++ b/litedram/init.py
@@ -506,7 +506,7 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
     elif phytype in ["A7DDRPHY", "K7DDRPHY", "V7DDRPHY"]:
         r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n"
         r += "#define SDRAM_PHY_DELAYS 32\n"
-        r += "#define SDRAM_PHY_BITSLIPS 16\n"
+        r += "#define SDRAM_PHY_BITSLIPS 8\n"
     elif phytype in ["ECP5DDRPHY"]:
         r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/4\n"
         r += "#define SDRAM_PHY_DELAYS 8\n"
diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py
index ed48ae8..73cfbbf 100644
--- a/litedram/phy/s7ddrphy.py
+++ b/litedram/phy/s7ddrphy.py
@@ -511,7 +511,7 @@ class S7DDRPHY(Module, AutoCSR):
             dq_bitslip = BitSlip(8,
                 rst    = self._dly_sel.storage[i//8] & self._rdly_dq_bitslip_rst.re,
                 slp    = self._dly_sel.storage[i//8] & self._rdly_dq_bitslip.re,
-                cycles = 2)
+                cycles = 1)
             self.submodules += dq_bitslip
             self.comb += dq_bitslip.i.eq(dq_i_data)
             self.comb += [