From c3ec0ab079db85a50c2cc2cc754fb8216a2eab9a Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Sat, 6 Nov 2021 07:33:31 +0700 Subject: [PATCH] W9825G6KH6 seems to use 8192 refresh cycles not 8000 --- litedram/modules.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/modules.py b/litedram/modules.py index 46a9966..5f2d782 100644 --- a/litedram/modules.py +++ b/litedram/modules.py @@ -541,7 +541,7 @@ class W9825G6KH6(SDRModule): nrows = 8192 ncols = 512 # timings - technology_timings = _TechnologyTimings(tREFI=64e6/8000, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10)) + technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10)) speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 60), tFAW=None, tRAS=42)} # DDR ----------------------------------------------------------------------------------------------