diff --git a/test/test_lpddr5.py b/test/test_lpddr5.py
index 08d84be..e27250c 100644
--- a/test/test_lpddr5.py
+++ b/test/test_lpddr5.py
@@ -198,7 +198,7 @@ class LPDDR5Tests(unittest.TestCase):
                     'ca2': '00' '00' '1000 0010 0000',
                     'ca3': '00' '00' '1000 0010 0000',
                     'ca4': '00' '00' '0000 0000 0000',
-                    'ca5': '00' '00' '1000 0000 0000',
+                    'ca5': '00' '00' '1000 0010 0000',
                     'ca6': '00' '00' '0000 0000 0000',
                 }
             },
@@ -228,7 +228,7 @@ class LPDDR5Tests(unittest.TestCase):
                     'ca2': '00' '00' '1000 0010 0000',
                     'ca3': '00' '00' '1010 0010 1000',
                     'ca4': '00' '00' '0010 0000 1000',
-                    'ca5': '00' '00' '1000 0000 0000',
+                    'ca5': '00' '00' '1000 0010 0000',
                     'ca6': '00' '00' '0000 0000 0000',
                 }
             },
@@ -261,7 +261,7 @@ class LPDDR5Tests(unittest.TestCase):
                             'ca1': '00' '00' '0010 0000 1000',
                             'ca2': '00' '00'f'{w1} 0010 {w2}',
                             'ca3': '00' '00' '1000 0010 0000',
-                            'ca4': '00' '00' '1000 0000 0000',
+                            'ca4': '00' '00' '1000 0010 0000',
                             'ca5': '00' '00' '0000 0000 0000',
                             'ca6': '00' '00' '0000 0000 0000',
                         }
@@ -308,8 +308,8 @@ class LPDDR5Tests(unittest.TestCase):
                             'ca1': '00' '0000' '0001 0011 1110 0000 0001 0101 0000 0000 0001',
                             'ca2': '00' '0000'f'1001 {mw} 1000 0000 0001 0000 1001 0001 0001',
                             'ca3': '00' '0000' '1011 1001 1010 0010 0010 1011 1011 0000 0000',
-                            'ca4': '00' '0000' '0000 0000 1010 0010 001x 1100 0010 0010 0010',
-                            'ca5': '00' '0000' '1011 0000 1001 0010 001x 0001 0001 0010 0010',
+                            'ca4': '00' '0000' '0000 1000 1010 0010 001x 1100 0010 0010 0010',
+                            'ca5': '00' '0000' '1011 0000 1001 0010 001x 0001 1001 0010 0010',
                             'ca6': '00' '0000' '0010 0001 1101 0001 0010 1110 0001 0010 0010',
                         }
                     },
@@ -516,7 +516,7 @@ class LPDDR5Tests(unittest.TestCase):
                             # tWCKENL_WR starts counting from first command (CAS) so we add command latency,
                             # then preamble, then toggle for the whole burst, then postamble for tWCKPST=2.5tCK
                             # (but for now we assume that WCK is never disabled)
-                            "wck0": "0000 0000" + wck_preamble + "10 10" * (16//4) + "10 10 1" + "0 10" + "10 10"*2,
+                            "wck0": "0000 0000" + wck_preamble + "10 10" * (16//4) + "10 10 1" + "0 10" + "00 00"*2,
                         },
                     },
                     chunk_size=4,