From c9954744df2a60d842f5a0d2d5bbd199fe87a7a8 Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Tue, 24 Aug 2021 17:32:06 +0200 Subject: [PATCH] lpddr5: wck sync at every transaction Signed-off-by: Alessandro Comodi --- litedram/init.py | 2 +- litedram/phy/lpddr5/basephy.py | 22 ++++++++++++++++++---- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/litedram/init.py b/litedram/init.py index 3851ce4..1269436 100644 --- a/litedram/init.py +++ b/litedram/init.py @@ -704,7 +704,7 @@ def get_lpddr5_phy_init_sequence(phy_settings, timing_settings): mr[18] = reg([ (0, 3, rzq_map[wck_odt]), (3, 1, 0), # WCK low frequency mode - (4, 1, 1), # WCK always on mode enabled + (4, 1, 0), # WCK always on mode enabled (6, 1, 0), # WCK2CK leveling diabled (7, 1, {2: 1, 4: 0}[wck_ck_ratio]), ]) diff --git a/litedram/phy/lpddr5/basephy.py b/litedram/phy/lpddr5/basephy.py index 41ea0de..286a2f9 100644 --- a/litedram/phy/lpddr5/basephy.py +++ b/litedram/phy/lpddr5/basephy.py @@ -121,7 +121,6 @@ def get_frange(twck, wck_ck_ratio): return frange raise ValueError - class LPDDR5PHY(Module, AutoCSR): """Core logic of LPDDR5 PHY @@ -295,9 +294,6 @@ class LPDDR5PHY(Module, AutoCSR): # WL = tWCKENL_WR - 1 + tWCKPRE_Static + tWCKPRE_Toggle_WR # RL = tWCKENL_RD - 1 + tWCKPRE_Static + tWCKPRE_Toggle_RD (without Byte Mode, nor Read DBI/Read Data Copy) wck_sync_done = Signal() - self.sync += If(self.adapter.wck_sync != 0, wck_sync_done.eq(1)) - self.comb += self.adapter.wck_sync_done.eq(wck_sync_done) - wck_sync = TappedDelayLine( signal = self.adapter.wck_sync, ntaps = max(1, max(frange.t_wckenl_wr, frange.t_wckenl_rd) + frange.t_wckpre_static), @@ -428,6 +424,24 @@ class LPDDR5PHY(Module, AutoCSR): self.dfi.p0.rddata_valid.eq(rddata_converter.source.valid), ] + self.wck_sync_state = Signal(2) + self.sync += If(self.adapter.wck_sync != 0, + wck_sync_done.eq(1), + self.wck_sync_state.eq(self.adapter.wck_sync) + ).Elif(self.wck_sync_state == WCKSyncType.RD, + If(reduce(or_, rddata_en.taps[0:rddata_start+burst_ck_cycles]) == 0, + wck_sync_done.eq(0), + self.wck_sync_state.eq(0b00), + ) + ).Elif(self.wck_sync_state == WCKSyncType.WR, + If(reduce(or_, wrdata_en.taps[0:wrtap+burst_ck_cycles]) == 0, + wck_sync_done.eq(0), + self.wck_sync_state.eq(0b00), + ) + ) + + self.comb += self.adapter.wck_sync_done.eq(wck_sync_done) + for bit in range(self.databits): # output wrdata = [wrdata_ck[i * self.databits + bit] for i in range(2*wck_ck_ratio)]