From c9f2e30dcc400c5064d5bf7243a0b95812149c62 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 13 Jul 2018 17:32:24 +0200 Subject: [PATCH] core/controller: add simulation workaround for 1:2 ddr3 phy --- litedram/core/controller.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litedram/core/controller.py b/litedram/core/controller.py index 9f9551f..16a6a6c 100644 --- a/litedram/core/controller.py +++ b/litedram/core/controller.py @@ -54,6 +54,9 @@ class LiteDRAMController(Module): bank_machines.append(bank_machine) self.submodules += bank_machine self.comb += getattr(self.interface, "bank"+str(i)).connect(bank_machine.req) + # FIXME: simulation workaround + if phy_settings.memtype == "DDR3" and phy_settings.nphases == 2: + self.comb += bank_machine.req.adr[-1].eq(0) self.submodules.multiplexer = Multiplexer(settings, bank_machines,