From ca17cfd83d69c695a9252e7e9159a0a5ba80fdb8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 10 Feb 2020 09:56:36 +0100 Subject: [PATCH] frontend/wishbone: round port_data_width to lowest power of 2 (required for ECC cases) --- litedram/frontend/wishbone.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/litedram/frontend/wishbone.py b/litedram/frontend/wishbone.py index c914c54..5286245 100644 --- a/litedram/frontend/wishbone.py +++ b/litedram/frontend/wishbone.py @@ -3,6 +3,8 @@ """Wishbone frontend for LiteDRAM""" +from math import log2 + from migen import * from litex.soc.interconnect import stream @@ -13,7 +15,7 @@ from litex.soc.interconnect import stream class LiteDRAMWishbone2Native(Module): def __init__(self, wishbone, port, base_address=0x00000000): wishbone_data_width = len(wishbone.dat_w) - port_data_width = len(port.wdata.data) + port_data_width = 2**int(log2(len(port.wdata.data))) # Round to lowest power 2 assert wishbone_data_width >= port_data_width # # #