From ca82ac18d088401b8e2793e611af477d92cc5733 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 9 Nov 2018 15:32:49 +0100
Subject: [PATCH] frontend/wishbone: add LiteDRAMWishbone2AXI

---
 litedram/frontend/wishbone.py | 52 +++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/litedram/frontend/wishbone.py b/litedram/frontend/wishbone.py
index 00770fd..5a49747 100644
--- a/litedram/frontend/wishbone.py
+++ b/litedram/frontend/wishbone.py
@@ -48,3 +48,55 @@ class LiteDRAMWishbone2Native(Module):
             port.wdata.data.eq(wishbone.dat_w),
             wishbone.dat_r.eq(port.rdata.data)
         ]
+
+class LiteDRAMWishbone2AXI(Module):
+    def __init__(self, wishbone, port):
+
+        # # #
+
+        ashift = log2_int(port.data_width//8)
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        fsm.act("IDLE",
+            If(wishbone.cyc & wishbone.stb,
+                If(wishbone.we,
+                    NextValue(port.aw.valid, 1),
+                    NextValue(port.w.valid, 1),
+                    NextState("WRITE")
+                ).Else(
+                    NextValue(port.ar.valid, 1),
+                    NextState("READ")
+                )
+            )
+        )
+        fsm.act("WRITE",
+            port.aw.addr[ashift:].eq(wishbone.adr),
+            port.w.last.eq(1),
+            port.w.data.eq(wishbone.dat_w),
+            port.w.strb.eq(wishbone.sel),
+            If(port.aw.ready,
+                NextValue(port.aw.valid, 0)
+            ),
+            If(port.w.ready,
+                NextValue(port.w.valid, 0)
+            ),
+            If(port.b.valid,
+                port.b.ready.eq(1),
+                wishbone.ack.eq(1),
+                wishbone.err.eq(port.b.resp != 0b00),
+                NextState("IDLE")
+            )
+        )
+        fsm.act("READ",
+            port.ar.addr[ashift:].eq(wishbone.adr),
+            If(port.ar.ready,
+                NextValue(port.ar.valid, 0)
+            ),
+            If(port.r.valid,
+                port.r.ready.eq(1),
+                wishbone.dat_r.eq(port.r.data),
+                wishbone.ack.eq(1),
+                wishbone.err.eq(port.r.resp != 0b10),
+                NextState("IDLE")
+            )
+        )