diff --git a/litedram/phy/model.py b/litedram/phy/model.py
index bd8cbb3..b95abbf 100644
--- a/litedram/phy/model.py
+++ b/litedram/phy/model.py
@@ -15,7 +15,7 @@ from operator import or_
 
 
 class Bank(Module):
-    def __init__(self, data_width, nrows, ncols, burst_length):
+    def __init__(self, data_width, nrows, ncols, burst_length, we_granularity):
         self.activate = Signal()
         self.activate_row = Signal(max=nrows)
         self.precharge = Signal()
@@ -44,13 +44,17 @@ class Bank(Module):
 
         self.specials.mem = mem = Memory(data_width, nrows*ncols//burst_length)
         self.specials.write_port = write_port = mem.get_port(write_capable=True,
-                                                             we_granularity=8)
+                                                             we_granularity=we_granularity)
         self.specials.read_port = read_port = mem.get_port(async_read=True)
         self.comb += [
             If(active,
                 write_port.adr.eq(row*ncols | self.write_col),
                 write_port.dat_w.eq(self.write_data),
-                write_port.we.eq(Replicate(self.write, data_width//8) & ~self.write_mask),
+                If(we_granularity,
+                    write_port.we.eq(Replicate(self.write, data_width//8) & ~self.write_mask),
+                ).Else(
+                    write_port.we.eq(self.write),
+                ),
                 If(self.read,
                     read_port.adr.eq(row*ncols | self.read_col),
                     self.read_data.eq(read_port.dat_r)
@@ -92,7 +96,7 @@ class DFIPhase(Module):
 
 
 class SDRAMPHYModel(Module):
-    def __init__(self, module, settings):
+    def __init__(self, module, settings, we_granularity=8):
         if settings.memtype in ["SDR"]:
             burst_length = settings.nphases*1  # command multiplication*SDR
         elif settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
@@ -120,7 +124,7 @@ class SDRAMPHYModel(Module):
         self.submodules += phases
 
         # banks
-        banks = [Bank(data_width, nrows, ncols, burst_length) for i in range(nbanks)]
+        banks = [Bank(data_width, nrows, ncols, burst_length, we_granularity) for i in range(nbanks)]
         self.submodules += banks
 
         # connect DFI phases to banks (cmds, write datapath)
diff --git a/test/bist_async_tb.py b/test/bist_async_tb.py
index 365881b..0710f61 100755
--- a/test/bist_async_tb.py
+++ b/test/bist_async_tb.py
@@ -17,9 +17,9 @@ from litedram.phy.model import SDRAMPHYModel
 
 class SimModule(SDRAMModule):
     # geometry
-    nbanks = 4
+    nbanks = 2
     nrows  = 2048
-    ncols  = 4
+    ncols  = 2
     # timings
     tRP   = 1
     tRCD  = 1
@@ -45,7 +45,8 @@ class TB(Module):
             read_latency=4,
             write_latency=0
         )
-        self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings)
+        self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings, we_granularity=0)
+
         # controller
         self.submodules.controller = LiteDRAMController(
                                          phy_settings,
@@ -55,6 +56,7 @@ class TB(Module):
         self.comb += self.controller.dfi.connect(self.sdrphy.dfi)
         self.submodules.crossbar = LiteDRAMCrossbar(self.controller.interface,
                                                     self.controller.nrowbits)
+
         # write port
         write_crossbar_port = self.crossbar.get_port()
         write_user_port = LiteDRAMPort(write_crossbar_port.aw,
@@ -68,9 +70,12 @@ class TB(Module):
         read_user_port = LiteDRAMPort(read_crossbar_port.aw,
                                       read_crossbar_port.dw,
                                       cd="read")
+
         # read port
         self.submodules += LiteDRAMPortCDC(read_user_port,
                                            read_crossbar_port)
+
+        # generator / checker
         self.submodules.generator = LiteDRAMBISTGenerator(write_user_port)
         self.submodules.checker = LiteDRAMBISTChecker(read_user_port)
 
@@ -78,6 +83,13 @@ class TB(Module):
 def main_generator(dut):
     for i in range(100):
         yield
+    # init
+    yield dut.generator.reset.storage.eq(1)
+    yield dut.checker.reset.storage.eq(1)
+    yield
+    yield dut.generator.reset.storage.eq(0)
+    yield dut.checker.reset.storage.eq(0)
+    yield
     # write
     yield dut.generator.base.storage.eq(16)
     yield dut.generator.length.storage.eq(16)