From cc434c407b33ff15a028c629c13d8869b1c13d60 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 31 May 2023 19:07:06 +0200 Subject: [PATCH] frontend/adapter: Add early_cmd_ready parameter to keep default behaviour to False but allow enabling it in Avalon Frontend. --- litedram/frontend/adapter.py | 9 +++++---- litedram/frontend/avalon.py | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/litedram/frontend/adapter.py b/litedram/frontend/adapter.py index 8530279..dc3fc41 100644 --- a/litedram/frontend/adapter.py +++ b/litedram/frontend/adapter.py @@ -70,7 +70,7 @@ class LiteDRAMNativePortDownConverter(Module): - A read from the user generates N reads to the controller and returned datas are regrouped in a single data presented to the user. """ - def __init__(self, port_from, port_to, reverse=False): + def __init__(self, port_from, port_to, reverse=False, early_cmd_ready=False): assert port_from.clock_domain == port_to.clock_domain assert port_from.data_width > port_to.data_width assert port_from.mode == port_to.mode @@ -88,7 +88,7 @@ class LiteDRAMNativePortDownConverter(Module): self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", - port_from.cmd.ready.eq(1), + port_from.cmd.ready.eq(early_cmd_ready), If(port_from.cmd.valid, NextValue(cmd_count, 0), NextValue(cmd_addr, port_from.cmd.addr), @@ -103,6 +103,7 @@ class LiteDRAMNativePortDownConverter(Module): If(port_to.cmd.ready, NextValue(cmd_count, cmd_count + 1), If(cmd_count == (ratio - 1), + port_from.cmd.ready.eq(~early_cmd_ready), NextState("IDLE") ) ) @@ -362,7 +363,7 @@ class LiteDRAMNativePortUpConverter(Module): # LiteDRAMNativePortConverter ---------------------------------------------------------------------- class LiteDRAMNativePortConverter(Module): - def __init__(self, port_from, port_to, reverse=False): + def __init__(self, port_from, port_to, reverse=False, early_cmd_ready=False): assert port_from.clock_domain == port_to.clock_domain assert port_from.mode == port_to.mode @@ -372,7 +373,7 @@ class LiteDRAMNativePortConverter(Module): if ratio > 1: # DownConverter - self.submodules.converter = LiteDRAMNativePortDownConverter(port_from, port_to, reverse) + self.submodules.converter = LiteDRAMNativePortDownConverter(port_from, port_to, reverse, early_cmd_ready) elif ratio < 1: # UpConverter self.submodules.converter = LiteDRAMNativePortUpConverter(port_from, port_to, reverse) diff --git a/litedram/frontend/avalon.py b/litedram/frontend/avalon.py index e54838a..e6440f4 100644 --- a/litedram/frontend/avalon.py +++ b/litedram/frontend/avalon.py @@ -44,7 +44,7 @@ class LiteDRAMAvalonMM2Native(LiteXModule): address_width = port.address_width + addr_shift, data_width = avalon_data_width ) - self.converter = LiteDRAMNativePortConverter(new_port, port) + self.converter = LiteDRAMNativePortConverter(new_port, port, early_cmd_ready=True) port = new_port # # #