From c9b8db5dc9d8dcba54d3ee7250ee44c6f50feb62 Mon Sep 17 00:00:00 2001 From: bunnie Date: Tue, 21 Aug 2018 17:28:42 +0800 Subject: [PATCH 1/2] i think there's a missing "self" in the params --- litedram/common.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/common.py b/litedram/common.py index 9a4ed42..65218b7 100644 --- a/litedram/common.py +++ b/litedram/common.py @@ -26,7 +26,7 @@ class PhySettings: self.cwl = cwl # Optional DDR3 electrical settings - def add_electrical_settings(rtt_nom, rtt_wr, ron): + def add_electrical_settings(self, rtt_nom, rtt_wr, ron): assert self.memtype == "DDR3" self.rtt_nom = rtt_nom # Non-Writes on-die termination impedance self.rtt_wr = rtt_wr # Writes on-die termination impedance From 818c6785f0cba0a92b8910ac105a912f1478a158 Mon Sep 17 00:00:00 2001 From: bunnie Date: Tue, 21 Aug 2018 17:59:54 +0800 Subject: [PATCH 2/2] update module settings to reflect latest changes --- litedram/modules.py | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/litedram/modules.py b/litedram/modules.py index 8126dc2..f52fe52 100644 --- a/litedram/modules.py +++ b/litedram/modules.py @@ -356,3 +356,29 @@ class MT18KSF1G72HZ(SDRAMModule): tWR = tWR_1600 tRFC = tRFC_1600 tFAW = tFAW_1600 + + +class K4B2G1646FBCK0(SDRAMModule): ### TODO: optimize and revalidate all timings, at cold and hot temperatures + memtype = "DDR3" + # geometry + nbanks = 8 + nrows = 16384 + ncols = 1024 + # speedgrade invariant timings + tREFI = 7800 # 3900 refresh more often at 85C+ + tWTR = (14, 35) + tCCD = (4, None) + tRRD = 10 # 4 * clk = 10ns + # speedgrade related timings + # DDR3-1600 + tRP_1600 = 13.125 + tRCD_1600 = 13.125 + tWR_1600 = 35 # this is hard-coded in MR0 to be 14 cycles, 14 * 2.5 = 35, see sdram_init.py@L224 + tRFC_1600 = 160 + tFAW_1600 = (None, 40) + # API retro-compatibility + tRP = tRP_1600 + tRCD = tRCD_1600 + tWR = tWR_1600 + tRFC = tRFC_1600 + tFAW = tFAW_1600