From ce72e5b3fe7cd5d8100ca095badf9ac357b2323a Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 2 Oct 2021 14:51:46 +0200
Subject: [PATCH] modules: Add MT40A2G8/MT40A2G16.

---
 litedram/modules.py | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index 309d4d6..1828967 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -904,6 +904,26 @@ class MT40A1G8(DDR4Module):
     }
     speedgrade_timings["default"] = speedgrade_timings["2400"]
 
+class MT40A2G8(DDR4Module):
+    # geometry
+    ngroupbanks = 4
+    ngroups     = 4
+    nbanks      = ngroups * ngroupbanks
+    nrows       = 131072
+    ncols       = 1024
+    # timings
+    trefi = {"1x": 64e6/8192,   "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
+    trfc  = {"1x": (None, 350), "2x": (None, 260),   "4x": (None, 160)}
+    technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6.4), tZQCS=(128, 80))
+    speedgrade_timings = {
+        "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=32),
+        "2666": _SpeedgradeTimings(tRP=13.50, tRCD=13.50, tWR=15, tRFC=trfc, tFAW=(20, 21), tRAS=32),
+    }
+    speedgrade_timings["default"] = speedgrade_timings["2400"]
+
+class MT40A2G16(MT40A2G8):
+    pass # TwinDie MT40A2G8.
+
 class MT40A256M16(DDR4Module):
     # geometry
     ngroupbanks = 4