From cf45ca48bcd41b0060393a298dab21d891006049 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 7 Sep 2020 18:50:01 +0200
Subject: [PATCH] s7ddrphy/usddrphy: add cmd_delay parameter and pass
 cmd_latency/cmd_delay to PhySettings/Software.

---
 litedram/common.py       | 3 ++-
 litedram/init.py         | 4 ++++
 litedram/phy/s7ddrphy.py | 3 +++
 litedram/phy/usddrphy.py | 5 ++++-
 4 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/litedram/common.py b/litedram/common.py
index 311843f..a84a71a 100644
--- a/litedram/common.py
+++ b/litedram/common.py
@@ -176,7 +176,8 @@ class PhySettings(Settings):
                  nphases,
                  rdphase, wrphase,
                  rdcmdphase, wrcmdphase,
-                 cl, read_latency, write_latency, nranks=1, cwl=None):
+                 cl, read_latency, write_latency, nranks=1, cwl=None,
+                 cmd_latency=None, cmd_delay=None):
         self.set_attributes(locals())
         self.cwl = cl if cwl is None else cwl
         self.is_rdimm = False
diff --git a/litedram/init.py b/litedram/init.py
index d93d5c8..f224de0 100644
--- a/litedram/init.py
+++ b/litedram/init.py
@@ -485,6 +485,10 @@ def get_sdram_phy_c_header(phy_settings, timing_settings):
     r += "#define SDRAM_PHY_XDR "+str(1 if phy_settings.memtype == "SDR" else 2) + "\n"
     r += "#define SDRAM_PHY_DATABITS "+str(phy_settings.databits) + "\n"
     r += "#define SDRAM_PHY_PHASES "+str(nphases)+"\n"
+    if phy_settings.cmd_latency is not None:
+        r += "#define SDRAM_PHY_CMD_LATENCY "+str(phy_settings.cmd_latency)+"\n"
+    if phy_settings.cmd_delay is not None:
+        r += "#define SDRAM_PHY_CMD_DELAY "+str(phy_settings.cmd_delay)+"\n"
 
     # Define Read/Write Leveling capability
     if phytype in ["USDDRPHY", "USPDDRPHY", "K7DDRPHY", "V7DDRPHY"]:
diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py
index 78e59a4..1e548f8 100644
--- a/litedram/phy/s7ddrphy.py
+++ b/litedram/phy/s7ddrphy.py
@@ -27,6 +27,7 @@ class S7DDRPHY(Module, AutoCSR):
         sys_clk_freq     = 100e6,
         iodelay_clk_freq = 200e6,
         cmd_latency      = 0,
+        cmd_delay        = None,
         interface_type   = "NETWORKING"):
         assert not (memtype == "DDR3" and nphases == 2)
         assert interface_type in ["NETWORKING", "MEMORY"]
@@ -101,6 +102,8 @@ class S7DDRPHY(Module, AutoCSR):
             cwl           = cwl - cmd_latency,
             read_latency  = 2 + cl_sys_latency + iserdese2_latency[interface_type] + 2,
             write_latency = cwl_sys_latency,
+            cmd_latency   = cmd_latency,
+            cmd_delay     = cmd_delay,
         )
 
         # DFI Interface ----------------------------------------------------------------------------
diff --git a/litedram/phy/usddrphy.py b/litedram/phy/usddrphy.py
index 881e375..d3f37ac 100644
--- a/litedram/phy/usddrphy.py
+++ b/litedram/phy/usddrphy.py
@@ -26,6 +26,7 @@ class USDDRPHY(Module, AutoCSR):
         sys_clk_freq     = 100e6,
         iodelay_clk_freq = 200e6,
         cmd_latency      = 1,
+        cmd_delay        = None,
         is_rdimm         = False):
         phytype     = self.__class__.__name__
         device      = {"USDDRPHY": "ULTRASCALE", "USPDDRPHY": "ULTRASCALE_PLUS"}[phytype]
@@ -93,7 +94,9 @@ class USDDRPHY(Module, AutoCSR):
             cl            = cl,
             cwl           = cwl - cmd_latency,
             read_latency  = 2 + cl_sys_latency + 1 + 2,
-            write_latency = cwl_sys_latency
+            write_latency = cwl_sys_latency,
+            cmd_latency   = cmd_latency,
+            cmd_delay     = cmd_delay,
         )
 
         if is_rdimm: