From cff8500f524a5b1761dd6be090a42b4854620a37 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 8 Sep 2022 16:03:39 +0200 Subject: [PATCH] phy/gw2ddrphy: Add explicit TXCLK_POL and set it to 1 for DQS. --- litedram/phy/gw2ddrphy.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/litedram/phy/gw2ddrphy.py b/litedram/phy/gw2ddrphy.py index a0c037b..e33fb1e 100644 --- a/litedram/phy/gw2ddrphy.py +++ b/litedram/phy/gw2ddrphy.py @@ -195,6 +195,7 @@ class GW2DDRPHY(Module, AutoCSR): pad_oddrx2f = Signal() pad_clk = Signal() self.specials += Instance("OSER4", + p_TXCLK_POL = 0b0, i_RESET = ResetSignal("sys"), i_PCLK = ClockSignal("sys"), i_FCLK = ClockSignal("sys2x"), @@ -238,6 +239,7 @@ class GW2DDRPHY(Module, AutoCSR): for i in range(len(pad)): pad_oddrx2f = Signal() self.specials += Instance("OSER4", + p_TXCLK_POL = 0b0, i_RESET = ResetSignal("sys"), i_PCLK = ClockSignal("sys"), i_FCLK = ClockSignal("sys2x"), @@ -320,6 +322,7 @@ class GW2DDRPHY(Module, AutoCSR): self.specials += [ Instance("OSER4_MEM", p_TCLK_SOURCE = "DQSW", + p_TXCLK_POL = 0b1, i_RESET = ResetSignal("sys"), i_PCLK = ClockSignal("sys"), i_FCLK = ClockSignal("sys2x"), @@ -352,6 +355,7 @@ class GW2DDRPHY(Module, AutoCSR): self.sync += Case(bl8_chunk, dm_bl8_cases) self.specials += Instance("OSER4_MEM", p_TCLK_SOURCE = "DQSW270", + p_TXCLK_POL = 0b0, i_RESET = ResetSignal("sys"), i_PCLK = ClockSignal("sys"), i_FCLK = ClockSignal("sys2x"), @@ -380,6 +384,7 @@ class GW2DDRPHY(Module, AutoCSR): self.specials += [ Instance("OSER4_MEM", p_TCLK_SOURCE = "DQSW270", + p_TXCLK_POL = 0b0, i_RESET = ResetSignal("sys"), i_PCLK = ClockSignal("sys"), i_FCLK = ClockSignal("sys2x"),