From d061e606119909a5ac2604f88d6d7f72a65c4ee0 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 16 Apr 2020 11:38:43 +0200
Subject: [PATCH] test/reference: update.

---
 test/reference/ddr3_init.h | 12 +++++++++---
 test/reference/ddr4_init.h | 13 ++++++++++---
 test/reference/sdr_init.h  |  7 ++++---
 3 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/test/reference/ddr3_init.h b/test/reference/ddr3_init.h
index 3006053..59952d0 100644
--- a/test/reference/ddr3_init.h
+++ b/test/reference/ddr3_init.h
@@ -4,7 +4,13 @@
 #include <generated/csr.h>
 #include <hw/flags.h>
 
-#define DFII_NPHASES 4
+#define SDRAM_PHY_K7DDRPHY
+#define SDRAM_PHY_PHASES 4
+#define SDRAM_PHY_WRITE_LEVELING_CAPABLE
+#define SDRAM_PHY_READ_LEVELING_CAPABLE
+#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2
+#define SDRAM_PHY_DELAYS 32
+#define SDRAM_PHY_BITSLIPS 8
 
 static void cdelay(int i);
 
@@ -39,14 +45,14 @@ __attribute__((unused)) static void command_p3(int cmd)
 
 #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
 
-const unsigned long sdram_dfii_pix_wrdata_addr[DFII_NPHASES] = {
+const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = {
 	CSR_SDRAM_DFII_PI0_WRDATA_ADDR,
 	CSR_SDRAM_DFII_PI1_WRDATA_ADDR,
 	CSR_SDRAM_DFII_PI2_WRDATA_ADDR,
 	CSR_SDRAM_DFII_PI3_WRDATA_ADDR
 };
 
-const unsigned long sdram_dfii_pix_rddata_addr[DFII_NPHASES] = {
+const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = {
 	CSR_SDRAM_DFII_PI0_RDDATA_ADDR,
 	CSR_SDRAM_DFII_PI1_RDDATA_ADDR,
 	CSR_SDRAM_DFII_PI2_RDDATA_ADDR,
diff --git a/test/reference/ddr4_init.h b/test/reference/ddr4_init.h
index 2f99c9d..4510afc 100644
--- a/test/reference/ddr4_init.h
+++ b/test/reference/ddr4_init.h
@@ -4,7 +4,14 @@
 #include <generated/csr.h>
 #include <hw/flags.h>
 
-#define DFII_NPHASES 4
+#define SDRAM_PHY_USDDRPHY
+#define SDRAM_PHY_PHASES 4
+#define SDRAM_PHY_WRITE_LEVELING_CAPABLE
+#define SDRAM_PHY_WRITE_LEVELING_REINIT
+#define SDRAM_PHY_READ_LEVELING_CAPABLE
+#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2
+#define SDRAM_PHY_DELAYS 512
+#define SDRAM_PHY_BITSLIPS 8
 
 static void cdelay(int i);
 
@@ -39,14 +46,14 @@ __attribute__((unused)) static void command_p3(int cmd)
 
 #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
 
-const unsigned long sdram_dfii_pix_wrdata_addr[DFII_NPHASES] = {
+const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = {
 	CSR_SDRAM_DFII_PI0_WRDATA_ADDR,
 	CSR_SDRAM_DFII_PI1_WRDATA_ADDR,
 	CSR_SDRAM_DFII_PI2_WRDATA_ADDR,
 	CSR_SDRAM_DFII_PI3_WRDATA_ADDR
 };
 
-const unsigned long sdram_dfii_pix_rddata_addr[DFII_NPHASES] = {
+const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = {
 	CSR_SDRAM_DFII_PI0_RDDATA_ADDR,
 	CSR_SDRAM_DFII_PI1_RDDATA_ADDR,
 	CSR_SDRAM_DFII_PI2_RDDATA_ADDR,
diff --git a/test/reference/sdr_init.h b/test/reference/sdr_init.h
index b091c7a..1e6ea49 100644
--- a/test/reference/sdr_init.h
+++ b/test/reference/sdr_init.h
@@ -4,7 +4,8 @@
 #include <generated/csr.h>
 #include <hw/flags.h>
 
-#define DFII_NPHASES 1
+#define SDRAM_PHY_GENSDRPHY
+#define SDRAM_PHY_PHASES 1
 
 static void cdelay(int i);
 
@@ -24,11 +25,11 @@ __attribute__((unused)) static void command_p0(int cmd)
 
 #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
 
-const unsigned long sdram_dfii_pix_wrdata_addr[DFII_NPHASES] = {
+const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = {
 	CSR_SDRAM_DFII_PI0_WRDATA_ADDR
 };
 
-const unsigned long sdram_dfii_pix_rddata_addr[DFII_NPHASES] = {
+const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = {
 	CSR_SDRAM_DFII_PI0_RDDATA_ADDR
 };