From d1089701d43231f32f5ec22d8f8a9027a58bee86 Mon Sep 17 00:00:00 2001
From: Ambroz Bizjak <abizjak.pro@gmail.com>
Date: Mon, 27 May 2019 19:29:57 +0200
Subject: [PATCH] modules/ddr3: add IS43TR16128B_125K

This is the chip that is actually on my Arty A7 100T (there is no mention of this chip in the Arty reference, which claims it is MT41K128M16JT-125).
---
 litedram/modules.py | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/litedram/modules.py b/litedram/modules.py
index 0b84e7d..0c128c3 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -310,6 +310,19 @@ class K4B2G1646F(SDRAMModule):
     speedgrade_timings["default"] = speedgrade_timings["1600"]
 
 
+class IS43TR16128B_125K(SDRAMModule):
+    memtype = "DDR3"
+    # geometry
+    nbanks = 8
+    nrows  = 16384
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6))
+    speedgrade_timings = {
+        "default": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=15, tRFC=160, tFAW=(None, 40), tRAS=35),
+    }
+
+
 # DDR3 (SO-DIMM)
 class MT8JTF12864(SDRAMModule):
     memtype = "DDR3"