From 4c9f184566bf9a0b53d4431b5e653afea512baf3 Mon Sep 17 00:00:00 2001 From: Michal Sieron Date: Mon, 9 Jan 2023 16:03:09 +0100 Subject: [PATCH 1/2] init: define SDRAM_PHY_[DDR3|DDR4|...] Will allow to ifdef code specific to some memory types like SPD reads. Signed-off-by: Michal Sieron --- litedram/init.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litedram/init.py b/litedram/init.py index 1755c1b..ed1b282 100644 --- a/litedram/init.py +++ b/litedram/init.py @@ -937,6 +937,7 @@ def get_sdram_phy_c_header(phy_settings, timing_settings): if phy_settings.bitslips > 0: r.define("SDRAM_PHY_BITSLIPS", phy_settings.bitslips) + r.define(f"SDRAM_PHY_{phy_settings.memtype}") if phy_settings.is_rdimm: assert phy_settings.memtype == "DDR4" r.define("SDRAM_PHY_DDR4_RDIMM") From 8fa325310a8636f50dd29383a0f4766765ec6d1b Mon Sep 17 00:00:00 2001 From: Michal Sieron Date: Mon, 9 Jan 2023 16:03:09 +0100 Subject: [PATCH 2/2] init: define SDRAM_PHY_SUPPORTED_MEMORY To use as a default value when one can't read SDRAM size from the SPD. Signed-off-by: Michal Sieron --- litedram/init.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/litedram/init.py b/litedram/init.py index ed1b282..5be9060 100644 --- a/litedram/init.py +++ b/litedram/init.py @@ -875,7 +875,7 @@ class CGenerator(list): self.append("}") -def get_sdram_phy_c_header(phy_settings, timing_settings): +def get_sdram_phy_c_header(phy_settings, timing_settings, geom_settings): r = CGenerator() r.header_guard("__GENERATED_SDRAM_PHY_H") r.include("") @@ -942,6 +942,12 @@ def get_sdram_phy_c_header(phy_settings, timing_settings): assert phy_settings.memtype == "DDR4" r.define("SDRAM_PHY_DDR4_RDIMM") + # litedram doesn't support multiple ranks + supported_memory = 2 ** (geom_settings.bankbits + + geom_settings.rowbits + + geom_settings.colbits) * phy_settings.databits // 8 + r.define("SDRAM_PHY_SUPPORTED_MEMORY", f"0x{supported_memory:016x}ULL") + r.newline() r += "void cdelay(int i);"