diff --git a/litedram/phy/gensdrphy.py b/litedram/phy/gensdrphy.py
index ebfc9fa..26a1621 100644
--- a/litedram/phy/gensdrphy.py
+++ b/litedram/phy/gensdrphy.py
@@ -33,11 +33,13 @@ class GENSDRPHY(Module):
     def __init__(self, pads):
         addressbits = len(pads.a)
         bankbits = len(pads.ba)
+        nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)
         databits = len(pads.dq)
 
         self.settings = PhySettings(
             memtype="SDR",
             dfi_databits=databits,
+            nranks=nranks,
             nphases=1,
             rdphase=0,
             wrphase=0,
@@ -48,7 +50,7 @@ class GENSDRPHY(Module):
             write_latency=0
         )
 
-        self.dfi = Interface(addressbits, bankbits, databits)
+        self.dfi = Interface(addressbits, bankbits, nranks, databits)
 
         # # #
 
diff --git a/litedram/phy/kusddrphy.py b/litedram/phy/kusddrphy.py
index 758c918..3095250 100644
--- a/litedram/phy/kusddrphy.py
+++ b/litedram/phy/kusddrphy.py
@@ -14,6 +14,7 @@ class KUSDDRPHY(Module, AutoCSR):
     def __init__(self, pads):
         addressbits = len(pads.a)
         bankbits = len(pads.ba)
+        nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)
         databits = len(pads.dq)
         nphases = 4
 
@@ -37,6 +38,7 @@ class KUSDDRPHY(Module, AutoCSR):
         self.settings = PhySettings(
             memtype="DDR3",
             dfi_databits=2*databits,
+            nranks=nranks,
             nphases=nphases,
             rdphase=0,
             wrphase=2,
@@ -48,7 +50,7 @@ class KUSDDRPHY(Module, AutoCSR):
             write_latency=2
         )
 
-        self.dfi = Interface(addressbits, bankbits, 2*databits, nphases)
+        self.dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases)
 
         # # #
 
diff --git a/litedram/phy/s6ddrphy.py b/litedram/phy/s6ddrphy.py
index b5077f5..6378072 100644
--- a/litedram/phy/s6ddrphy.py
+++ b/litedram/phy/s6ddrphy.py
@@ -33,6 +33,7 @@ class S6HalfRateDDRPHY(Module):
             raise NotImplementedError("S6HalfRateDDRPHY only supports DDR, LPDDR, DDR2 and DDR3")
         addressbits = len(pads.a)
         bankbits = len(pads.ba)
+        nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)
         databits = len(pads.dq)
         nphases = 2
 
@@ -40,6 +41,7 @@ class S6HalfRateDDRPHY(Module):
             self.settings = PhySettings(
                 memtype="DDR3",
                 dfi_databits=2*databits,
+                nranks=nranks,
                 nphases=nphases,
                 rdphase=0,
                 wrphase=1,
@@ -54,6 +56,7 @@ class S6HalfRateDDRPHY(Module):
             self.settings = PhySettings(
                 memtype=memtype,
                 dfi_databits=2*databits,
+                nranks=nranks,
                 nphases=nphases,
                 rdphase=0,
                 wrphase=1,
@@ -64,7 +67,7 @@ class S6HalfRateDDRPHY(Module):
                 write_latency=0
             )
 
-        self.dfi = Interface(addressbits, bankbits, 2*databits, nphases)
+        self.dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases)
         self.clk4x_wr_strb = Signal()
         self.clk4x_rd_strb = Signal()
 
@@ -407,12 +410,14 @@ class S6QuarterRateDDRPHY(Module):
 
         addressbits = len(pads.a)
         bankbits = len(pads.ba)
+        nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)
         databits = len(pads.dq)
         nphases = 4
 
         self.settings = PhySettings(
             memtype="DDR3",
             dfi_databits=2*databits,
+            nranks=nranks,
             nphases=nphases,
             rdphase=0,
             wrphase=1,
@@ -424,7 +429,7 @@ class S6QuarterRateDDRPHY(Module):
             write_latency=2//2
         )
 
-        self.dfi = Interface(addressbits, bankbits, 2*databits, nphases)
+        self.dfi = Interface(addressbits, bankbits, nranks, 2*databits, nphases)
         self.clk8x_wr_strb = half_rate_phy.clk4x_wr_strb
         self.clk8x_rd_strb = half_rate_phy.clk4x_rd_strb