From d2b2ba6d4b68eda9b4aaa27cc45ee6e09221d70f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 30 Sep 2021 17:56:40 +0200 Subject: [PATCH] modules/IS43TR16512B: Review timings, add 800/1066/1333 speedgrades. --- litedram/modules.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/litedram/modules.py b/litedram/modules.py index 194f25b..309d4d6 100644 --- a/litedram/modules.py +++ b/litedram/modules.py @@ -779,9 +779,12 @@ class IS43TR16512B(DDR3Module): nrows = 65536 ncols = 1024 # timings - technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6), tZQCS=(64, 80)) + technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 10), tZQCS=(64, 80)) speedgrade_timings = { - "1600": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=15, tRFC=(None, 260), tFAW=(None, 30), tRAS=35), + "800": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 350), tFAW=(None, 50), tRAS=37.5), + "1066": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=15, tRFC=(None, 350), tFAW=(None, 50), tRAS=37.5), + "1333": _SpeedgradeTimings(tRP=13.5, tRCD=13.5, tWR=15, tRFC=(None, 350), tFAW=(None, 50), tRAS=36), + "1600": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=15, tRFC=(None, 350), tFAW=(None, 50), tRAS=35), } speedgrade_timings["default"] = speedgrade_timings["1600"]