diff --git a/litedram/common.py b/litedram/common.py
index 13703b7..7a387cd 100644
--- a/litedram/common.py
+++ b/litedram/common.py
@@ -28,7 +28,10 @@ burst_lengths = {
 
 def get_default_cl_cwl(memtype, tck):
     f_to_cl_cwl = OrderedDict()
-    if memtype == "DDR2":
+    if memtype == "SDR":
+        f_to_cl_cwl[100e6] = (2, None)
+        f_to_cl_cwl[133e6] = (3, None)
+    elif memtype == "DDR2":
         f_to_cl_cwl[400e6]  = (3, 2)
         f_to_cl_cwl[533e6]  = (4, 3)
         f_to_cl_cwl[677e6]  = (5, 4)
@@ -49,7 +52,8 @@ def get_default_cl_cwl(memtype, tck):
     else:
         raise ValueError
     for f, (cl, cwl) in f_to_cl_cwl.items():
-        if tck >= 2/f:
+        m = 2 if "DDR" in memtype else 1
+        if tck >= m/f:
             return cl, cwl
     raise ValueError
 
diff --git a/litedram/phy/gensdrphy.py b/litedram/phy/gensdrphy.py
index 3d39a57..066b482 100644
--- a/litedram/phy/gensdrphy.py
+++ b/litedram/phy/gensdrphy.py
@@ -17,15 +17,17 @@ from litedram.phy.dfi import *
 # Generic SDR PHY ----------------------------------------------------------------------------------
 
 class GENSDRPHY(Module):
-    def __init__(self, pads, cl=2):
+    def __init__(self, pads, sys_clk_freq=100e6, cl=None):
         pads        = PHYPadsCombiner(pads)
         addressbits = len(pads.a)
         bankbits    = len(pads.ba)
         nranks      = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)
         databits    = len(pads.dq)
-        assert cl in [2, 3]
         assert databits%8 == 0
 
+        # Parameters -------------------------------------------------------------------------------
+        cl = get_default_cl(memtype="SDR", tck=1/sys_clk_freq) if cl is None else cl
+
         # PHY settings -----------------------------------------------------------------------------
         self.settings = PhySettings(
             phytype       = "GENSDRPHY",
@@ -85,7 +87,7 @@ class GENSDRPHY(Module):
 # Half-rate Generic SDR PHY ------------------------------------------------------------------------
 
 class HalfRateGENSDRPHY(Module):
-    def __init__(self, pads, cl=2):
+    def __init__(self, pads, sys_clk_freq=100e6, cl=None):
         pads        = PHYPadsCombiner(pads)
         addressbits = len(pads.a)
         bankbits    = len(pads.ba)
@@ -93,8 +95,12 @@ class HalfRateGENSDRPHY(Module):
         databits    = len(pads.dq)
         nphases     = 2
 
+
+        # Parameters -------------------------------------------------------------------------------
+        cl = get_default_cl(memtype="SDR", tck=1/sys_clk_freq) if cl is None else cl
+
         # FullRate PHY -----------------------------------------------------------------------------
-        full_rate_phy = GENSDRPHY(pads, cl)
+        full_rate_phy = GENSDRPHY(pads, 2*sys_clk_freq, cl)
         self.submodules += ClockDomainsRenamer("sys2x")(full_rate_phy)
 
         # Clocking ---------------------------------------------------------------------------------