diff --git a/litedram/gen.py b/litedram/gen.py
index cad9d2b..1a9e250 100644
--- a/litedram/gen.py
+++ b/litedram/gen.py
@@ -258,7 +258,7 @@ class LiteDRAMCore(SoCSDRAM):
             kwargs["with_uart"]            = False
             kwargs["with_timer"]           = False
             kwargs["with_ctrl"]            = False
-            kwargs["with_wishbone"]        = (cpu_type is None)
+            kwargs["with_wishbone"]        = (cpu_type != None)
         else:
            kwargs["l2_size"] = 0
         SoCSDRAM.__init__(self, platform, sys_clk_freq,