diff --git a/test/test_bist.py b/test/test_bist.py
index 5bd533b..958a487 100644
--- a/test/test_bist.py
+++ b/test/test_bist.py
@@ -84,6 +84,30 @@ class GenCheckCSRDriver:
             self.errors = (yield from self.module.errors.read())
 
 
+class DMAWriterDriver:
+    def __init__(self, dma):
+        self.dma = dma
+
+    def write(self, pattern):
+        yield self.dma.sink.valid.eq(1)
+        for adr, data in pattern:
+            yield self.dma.sink.address.eq(adr)
+            yield self.dma.sink.data.eq(data)
+            while not (yield self.dma.sink.ready):
+                yield
+            while (yield self.dma.sink.ready):
+                yield
+        yield self.dma.sink.valid.eq(0)
+
+    @staticmethod
+    def wait_complete(port, n):
+        for _ in range(n):
+            while not (yield port.wdata.ready):
+                yield
+            while (yield port.wdata.ready):
+                yield
+
+
 class TestBIST(unittest.TestCase):
     def setUp(self):
         # define common test data used for both generator and checker tests
@@ -271,7 +295,12 @@ class TestBIST(unittest.TestCase):
                     0x00000000,  # 0x1c
                 ],
             ),
+            "32bit_long_sequential": dict(pattern=[], expected=[0] * 64),
         }
+        for i in range(32):
+            data = self.pattern_test_data["32bit_long_sequential"]
+            data['pattern'].append((i, 64 + i))
+            data['expected'][i] = 64 + i
 
     def test_generator(self):
         def main_generator(dut):
@@ -591,3 +620,53 @@ class TestBIST(unittest.TestCase):
             "async": (7, 3),
         }
         run_simulation(dut, generators, clocks)
+
+    def dma_writer_test_pattern(self, pattern, mem_expected, data_width, **kwargs):
+        class DUT(Module):
+            def __init__(self):
+                self.port = LiteDRAMNativeWritePort(address_width=32, data_width=data_width)
+                self.submodules.dma = LiteDRAMDMAWriter(self.port, **kwargs)
+
+        dut = DUT()
+        driver = DMAWriterDriver(dut.dma)
+        mem = DRAMMemory(data_width, len(mem_expected))
+
+        generators = [
+            driver.write(pattern),
+            driver.wait_complete(dut.port, len(pattern)),
+            mem.write_handler(dut.port),
+        ]
+        run_simulation(dut, generators)
+        self.assertEqual(mem.mem, mem_expected)
+
+    def test_dma_writer_single(self):
+        pattern = [(0x04, 0xdeadc0de)]
+        mem_expected = [0] * 32
+        mem_expected[0x04] = 0xdeadc0de
+        self.dma_writer_test_pattern(pattern, mem_expected, data_width=32)
+
+    def test_dma_writer_multiple(self):
+        data = self.pattern_test_data["32bit"]
+        self.dma_writer_test_pattern(data["pattern"], data["expected"], data_width=32)
+
+    def test_dma_writer_sequential(self):
+        data = self.pattern_test_data["32bit_sequential"]
+        self.dma_writer_test_pattern(data["pattern"], data["expected"], data_width=32)
+
+    def test_dma_writer_long_sequential(self):
+        data = self.pattern_test_data["32bit_long_sequential"]
+        self.dma_writer_test_pattern(data["pattern"], data["expected"], data_width=32)
+
+    def test_dma_writer_no_fifo(self):
+        data = self.pattern_test_data["32bit_long_sequential"]
+        self.dma_writer_test_pattern(data["pattern"], data["expected"], data_width=32,
+                                     fifo_depth=1)
+
+    def test_dma_writer_fifo_buffered(self):
+        data = self.pattern_test_data["32bit_long_sequential"]
+        self.dma_writer_test_pattern(data["pattern"], data["expected"], data_width=32,
+                                     fifo_buffered=True)
+
+    def test_dma_writer_duplicates(self):
+        data = self.pattern_test_data["32bit_duplicates"]
+        self.dma_writer_test_pattern(data["pattern"], data["expected"], data_width=32)