From d89b17177ae675a493ae100de66f64a759f4b82c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 12 Feb 2019 11:26:48 +0100 Subject: [PATCH] modules/mt40a1g8: use _L (long) timings --- litedram/modules.py | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/litedram/modules.py b/litedram/modules.py index 3eea899..4781b21 100644 --- a/litedram/modules.py +++ b/litedram/modules.py @@ -373,15 +373,6 @@ class EDY4016A(SDRAMModule): class MT40A1G8(SDRAMModule): - # param | prodesign | this - # tFAW | 30n | 20, 21, 25 - # tRAS | 32n | 32 - # tRCD | 13.32n | 13.32, 13.5 - # tREFI | 7.8u | 7.825u - # tRFC | 350 | 350 - # tRP | 13.32n | 13.32, 13.5 - # tRRD | 3.3, 6.4 | 4, 4.9 - # tWTR | 2.5, 7.5 | 4, 7.5 memtype = "DDR4" # geometry ngroupbanks = 4 @@ -390,7 +381,7 @@ class MT40A1G8(SDRAMModule): nrows = 65536 ncols = 1024 # timings - technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2.5, 7.5), tCCD=(4, None), tRRD=(3.3, 6.4)) + technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6.4)) speedgrade_timings = { "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=350, tFAW=(20, 25), tRAS=32), "2666": _SpeedgradeTimings(tRP=13.50, tRCD=13.50, tWR=15, tRFC=350, tFAW=(20, 21), tRAS=32),