From d95c1fc5838de0dafe196ab89d5c6ce1de38105d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 16 Jan 2023 11:21:47 +0100 Subject: [PATCH] frontend/dma: Update omit signals in LiteDRAMDMAReader (Thanks @mohammadshahidzade). --- litedram/frontend/dma.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/frontend/dma.py b/litedram/frontend/dma.py index 0b28e1b..300ad42 100644 --- a/litedram/frontend/dma.py +++ b/litedram/frontend/dma.py @@ -104,7 +104,7 @@ class LiteDRAMDMAReader(Module, AutoCSR): self.submodules += fifo self.comb += [ - rdata.connect(fifo.sink, omit={"id", "resp"}), + rdata.connect(fifo.sink, omit={"id", "resp", "dest", "user"}), fifo.source.connect(source, omit={"ready"}), fifo.source.ready.eq(source.ready | ~enable), # Flush FIFO/Reservation counter when disabled. data_dequeued.eq(fifo.source.valid & fifo.source.ready)