From d9ec9882af8ce06fecab037711c35411125727ca Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 23 Sep 2021 18:55:51 +0200 Subject: [PATCH] frontend_fifo: Fix dram_data_cnt signal size. --- litedram/frontend/fifo.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/frontend/fifo.py b/litedram/frontend/fifo.py index ba6bc58..60d9b88 100644 --- a/litedram/frontend/fifo.py +++ b/litedram/frontend/fifo.py @@ -299,7 +299,7 @@ class LiteDRAMFIFO(Module): ) dram_data_inc = Signal() dram_data_dec = Signal() - dram_data_cnt = Signal(int(math.log2(depth))) + dram_data_cnt = Signal(int(math.log2(depth + writer_fifo_depth + reader_fifo_depth) + 1)) self.sync += dram_data_cnt.eq(dram_data_cnt + dram_data_inc - dram_data_dec) fsm.act("DRAM", # Increment DRAM Data Count on Pre-Converter's Sink cycle.