From da0671559699f2061c3143a725f543b213557346 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 19 Oct 2018 18:20:12 +0200 Subject: [PATCH] core/bankmachine: typo --- litedram/core/bankmachine.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py index 045ec4f..9171da1 100644 --- a/litedram/core/bankmachine.py +++ b/litedram/core/bankmachine.py @@ -83,7 +83,7 @@ class BankMachine(Module): # tWTP (write-to-precharge) controller write_latency = math.ceil(settings.phy.cwl / settings.phy.nphases) precharge_time = write_latency + settings.timing.tWR + settings.timing.tCCD # AL=0 - self.submodules.twtp_con = twtpcon = tXXDController(precharge_time) + self.submodules.twtpcon = twtpcon = tXXDController(precharge_time) self.comb += twtpcon.valid.eq(cmd.valid & cmd.ready & cmd.is_write) # tRC (activate-activate) controller