From da408a39829abce78df76db72b23bfbdf1f9e85b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 23 Sep 2019 09:05:54 +0200 Subject: [PATCH] gen: fix default csr_port_align value --- litedram/gen.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/gen.py b/litedram/gen.py index 5ae7c99..22e5e76 100644 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -248,7 +248,7 @@ class LiteDRAMCore(SoCSDRAM): def __init__(self, platform, core_config, **kwargs): platform.add_extension(get_common_ios()) sys_clk_freq = core_config["sys_clk_freq"] - csr_align = core_config.get("csr_port_align", "32") + csr_align = core_config.get("csr_port_align", 32) SoCSDRAM.__init__(self, platform, sys_clk_freq, cpu_type=core_config["cpu"], l2_size=16*core_config["sdram_module_nb"],