From 74279ea26a9355c97ceae412666c0f39841d669d Mon Sep 17 00:00:00 2001 From: Date: Fri, 10 Aug 2018 19:19:02 -0400 Subject: [PATCH 1/5] Enable auto-precharge --- litedram/core/bankmachine.py | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py index 5df27e0..1ba61d5 100644 --- a/litedram/core/bankmachine.py +++ b/litedram/core/bankmachine.py @@ -38,15 +38,18 @@ class BankMachine(Module): self.cmd = cmd = stream.Endpoint(cmd_request_rw_layout(a, ba)) # # # + auto_precharge = Signal() # Command buffer cmd_buffer_layout = [("we", 1), ("adr", len(req.adr))] - cmd_buffer = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth) - self.submodules += cmd_buffer + cmd_bufferPre = stream.SyncFIFO(cmd_buffer_layout, settings.cmd_buffer_depth) + cmd_buffer = stream.Buffer(cmd_buffer_layout) # 1 depth buffer to detect row change + self.submodules += cmd_buffer, cmd_bufferPre self.comb += [ - req.connect(cmd_buffer.sink, omit=["wdata_valid", "wdata_ready", + req.connect(cmd_bufferPre.sink, omit=["wdata_valid", "wdata_ready", "rdata_valid", "rdata_ready", "lock"]), + cmd_bufferPre.source.connect(cmd_buffer.sink), cmd_buffer.source.ready.eq(req.wdata_ready | req.rdata_valid), req.lock.eq(cmd_buffer.source.valid), ] @@ -75,7 +78,7 @@ class BankMachine(Module): If(sel_row_adr, cmd.a.eq(slicer.row(cmd_buffer.source.adr)) ).Else( - cmd.a.eq(slicer.col(cmd_buffer.source.adr)) + cmd.a.eq((auto_precharge << 10) | slicer.col(cmd_buffer.source.adr)) ) ] @@ -86,6 +89,15 @@ class BankMachine(Module): cmd.ready & cmd.is_write)) + # Auto Precharge + self.comb += [ + If(cmd_bufferPre.source.valid & cmd_buffer.source.valid, + If(slicer.row(cmd_bufferPre.source.adr) != slicer.row(cmd_buffer.source.adr), + auto_precharge.eq(self.precharge_timer.done & (track_close == 0)) + ) + ) + ] + # Control and command generation FSM self.submodules.fsm = fsm = FSM() fsm.act("REGULAR", @@ -106,7 +118,10 @@ class BankMachine(Module): req.rdata_valid.eq(cmd.ready), cmd.is_read.eq(1) ), - cmd.cas.eq(1) + cmd.cas.eq(1), + If(cmd.ready & auto_precharge, + NextState("AUTOPRECHARGE") + ) ) ).Else( NextState("PRECHARGE") @@ -151,3 +166,4 @@ class BankMachine(Module): ) fsm.delayed_enter("TRP", "ACTIVATE", settings.timing.tRP-1) fsm.delayed_enter("TRCD", "REGULAR", settings.timing.tRCD-1) + fsm.delayed_enter("AUTOPRECHARGE", "TRP", precharge_time-1) From 32069858ee0bc196a6a8a18a148c8824ceb87ad9 Mon Sep 17 00:00:00 2001 From: Date: Fri, 10 Aug 2018 20:48:30 -0400 Subject: [PATCH 2/5] When auto-precharging assert track_close --- litedram/core/bankmachine.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py index 1ba61d5..52173a6 100644 --- a/litedram/core/bankmachine.py +++ b/litedram/core/bankmachine.py @@ -144,6 +144,12 @@ class BankMachine(Module): ), track_close.eq(1) ) + fsm.act("AUTOPRECHARGE", + If(self.precharge_timer.done, + NextState("TRP") + ), + track_close.eq(1) + ) fsm.act("ACTIVATE", sel_row_adr.eq(1), track_open.eq(1), @@ -166,4 +172,3 @@ class BankMachine(Module): ) fsm.delayed_enter("TRP", "ACTIVATE", settings.timing.tRP-1) fsm.delayed_enter("TRCD", "REGULAR", settings.timing.tRCD-1) - fsm.delayed_enter("AUTOPRECHARGE", "TRP", precharge_time-1) From a4be642d568dcfaa8acfb718c01a79ab5dff79b9 Mon Sep 17 00:00:00 2001 From: Date: Tue, 14 Aug 2018 22:42:02 -0400 Subject: [PATCH 3/5] Fix multiple timings ignored --- litedram/core/multiplexer.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/litedram/core/multiplexer.py b/litedram/core/multiplexer.py index 70c3738..beac9b6 100644 --- a/litedram/core/multiplexer.py +++ b/litedram/core/multiplexer.py @@ -198,10 +198,12 @@ class Multiplexer(Module, AutoCSR): # tRRD timing (Row to Row delay) self.trrdcon = trrdcon = tXXDController(settings.timing.tRRD) + self.submodules += trrdcon self.comb += trrdcon.valid.eq(choose_cmd.accept() & choose_cmd.activate()) # tFAW timing (Four Activate Window) self.tfawcon = tfawcon = tFAWController(settings.timing.tFAW) + self.submodules += tfawcon self.comb += tfawcon.valid.eq(choose_cmd.accept() & choose_cmd.activate()) # RAS control @@ -210,6 +212,7 @@ class Multiplexer(Module, AutoCSR): # tCCD timing (Column to Column delay) self.tccdcon = tccdcon = tXXDController(settings.timing.tCCD) + self.submodules += tccdcon self.comb += tccdcon.valid.eq(choose_cmd.accept() & (choose_cmd.write() | choose_cmd.read())) # CAS control @@ -221,6 +224,7 @@ class Multiplexer(Module, AutoCSR): settings.timing.tWTR + # tCCD must be added since tWTR begins after the transfer is complete settings.timing.tCCD if settings.timing.tCCD is not None else 0) + self.submodules += twtrcon self.comb += twtrcon.valid.eq(choose_req.accept() & choose_req.write()) # Read/write turnaround From 16a852bda5104eeadb392ca121726c9d992b9f45 Mon Sep 17 00:00:00 2001 From: Date: Tue, 14 Aug 2018 23:23:24 -0400 Subject: [PATCH 4/5] Revert "core/refresher: synchronize valid" This reverts commit 6620a91a224b7a9fbc4cf4089c80be39763eb9b8 because it fails to issue a refresh command --- litedram/core/multiplexer.py | 2 +- litedram/core/refresher.py | 9 ++++----- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/litedram/core/multiplexer.py b/litedram/core/multiplexer.py index beac9b6..25fa6a3 100644 --- a/litedram/core/multiplexer.py +++ b/litedram/core/multiplexer.py @@ -329,7 +329,7 @@ class Multiplexer(Module, AutoCSR): fsm.act("REFRESH", steerer.sel[0].eq(STEER_REFRESH), refresher.cmd.ready.eq(1), - If(~refresher.cmd.valid, + If(refresher.cmd.last, NextState("READ") ) ) diff --git a/litedram/core/refresher.py b/litedram/core/refresher.py index be58b2c..904d671 100644 --- a/litedram/core/refresher.py +++ b/litedram/core/refresher.py @@ -45,16 +45,14 @@ class Refresher(Module): self.comb += self.timer.wait.eq(settings.with_refresh & ~self.timer.done) # Control FSM - cmd_valid = Signal() self.submodules.fsm = fsm = FSM() fsm.act("IDLE", If(self.timer.done, - cmd_valid.eq(1), NextState("WAIT_GRANT") ) ) fsm.act("WAIT_GRANT", - cmd_valid.eq(1), + cmd.valid.eq(1), If(cmd.ready, seq_start.eq(1), NextState("WAIT_SEQ") @@ -62,8 +60,9 @@ class Refresher(Module): ) fsm.act("WAIT_SEQ", If(seq_done, - cmd_valid.eq(0), + cmd.last.eq(1), NextState("IDLE") + ).Else( + cmd.valid.eq(1) ) ) - self.sync += cmd.valid.eq(cmd_valid) From 627cccde59d62467b78ed5e92119feb83eb94ab9 Mon Sep 17 00:00:00 2001 From: Date: Tue, 14 Aug 2018 23:55:01 -0400 Subject: [PATCH 5/5] Fix tCCD timing which watched the wrong command --- litedram/core/multiplexer.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/core/multiplexer.py b/litedram/core/multiplexer.py index 25fa6a3..3b64b89 100644 --- a/litedram/core/multiplexer.py +++ b/litedram/core/multiplexer.py @@ -213,7 +213,7 @@ class Multiplexer(Module, AutoCSR): # tCCD timing (Column to Column delay) self.tccdcon = tccdcon = tXXDController(settings.timing.tCCD) self.submodules += tccdcon - self.comb += tccdcon.valid.eq(choose_cmd.accept() & (choose_cmd.write() | choose_cmd.read())) + self.comb += tccdcon.valid.eq(choose_req.accept() & (choose_req.write() | choose_req.read())) # CAS control self.comb += cas_allowed.eq(tccdcon.ready)