From db54e325c8e604695fd0d0c4e16b409e6a693a3e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 24 Sep 2020 13:36:02 +0200 Subject: [PATCH] phy/usddrphy: reduce BitSlip cycles to 1 sys_clk. Increasing it to 2 hasn't been useful. --- litedram/init.py | 2 +- litedram/phy/usddrphy.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/litedram/init.py b/litedram/init.py index 597dea5..c16d4af 100644 --- a/litedram/init.py +++ b/litedram/init.py @@ -502,7 +502,7 @@ def get_sdram_phy_c_header(phy_settings, timing_settings): if phytype in ["USDDRPHY", "USPDDRPHY"]: r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n" r += "#define SDRAM_PHY_DELAYS 512\n" - r += "#define SDRAM_PHY_BITSLIPS 16\n" + r += "#define SDRAM_PHY_BITSLIPS 8\n" elif phytype in ["A7DDRPHY", "K7DDRPHY", "V7DDRPHY"]: r += "#define SDRAM_PHY_MODULES DFII_PIX_DATA_BYTES/2\n" r += "#define SDRAM_PHY_DELAYS 32\n" diff --git a/litedram/phy/usddrphy.py b/litedram/phy/usddrphy.py index 6bdbebf..0416cca 100644 --- a/litedram/phy/usddrphy.py +++ b/litedram/phy/usddrphy.py @@ -425,7 +425,7 @@ class USDDRPHY(Module, AutoCSR): dq_bitslip = BitSlip(8, rst = self._dly_sel.storage[i//8] & self._rdly_dq_bitslip_rst.re, slp = self._dly_sel.storage[i//8] & self._rdly_dq_bitslip.re, - cycles = 2) + cycles = 1) self.submodules += dq_bitslip self.specials += [ Instance("OSERDESE3",