From db9720387765bb44054fd953411a8c8dea84aeb7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 23 Sep 2019 12:55:14 +0200 Subject: [PATCH] gen: use SoCCore with_wishbone parameter, do more replace in yml files before passing config to LiteDRAMCore --- examples/arty.yml | 4 ++-- examples/genesys2.yml | 4 ++-- examples/nexys4ddr.yml | 4 ++-- litedram/gen.py | 10 ++++++++-- 4 files changed, 14 insertions(+), 8 deletions(-) diff --git a/examples/arty.yml b/examples/arty.yml index beb981e..acb7fdb 100644 --- a/examples/arty.yml +++ b/examples/arty.yml @@ -34,6 +34,6 @@ "user_ports_id_width": 32, # AXI identifier width # CSR Port ----------------------------------------------------------------- - "csr_expose": "no", # Expose CSR bus as I/Os - "csr_align" : 32, # CSR alignment + "csr_expose": "False", # Expose CSR bus as I/Os + "csr_align" : 32, # CSR alignment } diff --git a/examples/genesys2.yml b/examples/genesys2.yml index fb6338d..829b1c0 100644 --- a/examples/genesys2.yml +++ b/examples/genesys2.yml @@ -34,6 +34,6 @@ "user_ports_id_width": 32, # AXI identifier width # CSR Port ----------------------------------------------------------------- - "csr_expose": "no", # Expose CSR bus as I/Os - "csr_align" : 32, # CSR alignment + "csr_expose": "False", # Expose CSR bus as I/Os + "csr_align" : 32, # CSR alignment } diff --git a/examples/nexys4ddr.yml b/examples/nexys4ddr.yml index 5241e1c..1bc1808 100644 --- a/examples/nexys4ddr.yml +++ b/examples/nexys4ddr.yml @@ -29,6 +29,6 @@ "user_ports_id_width": 32, # AXI identifier width # CSR Port ----------------------------------------------------------------- - "csr_expose": "no", # Expose CSR bus as I/Os - "csr_align" : 32, # CSR alignment + "csr_expose": "False", # Expose CSR bus as I/Os + "csr_align" : 32, # CSR alignment } diff --git a/litedram/gen.py b/litedram/gen.py index 88483ce..cad9d2b 100644 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -249,14 +249,16 @@ class LiteDRAMCore(SoCSDRAM): platform.add_extension(get_common_ios()) sys_clk_freq = core_config["sys_clk_freq"] cpu_type = core_config["cpu"] + csr_expose = core_config.get("csr_expose", False) csr_align = core_config.get("csr_align", 32) - if cpu_type == "None": + if cpu_type is None: kwargs["integrated_rom_size"] = 0 kwargs["integrated_sram_size"] = 0 kwargs["l2_size"] = 0 kwargs["with_uart"] = False kwargs["with_timer"] = False kwargs["with_ctrl"] = False + kwargs["with_wishbone"] = (cpu_type is None) else: kwargs["l2_size"] = 0 SoCSDRAM.__init__(self, platform, sys_clk_freq, @@ -300,7 +302,7 @@ class LiteDRAMCore(SoCSDRAM): ] # CSR port - if core_config.get("csr_expose", "no") == "yes": + if csr_expose: csr_port = csr_bus.Interface( address_width=self.csr_address_width, data_width=self.csr_data_width) @@ -438,6 +440,10 @@ def main(): # Convert YAML elements to Python/LiteX for k, v in core_config.items(): + replaces = {"False": False, "True": True, "None": None} + for r in replaces.keys(): + if v == r: + core_config[k] = replaces[r] if "clk_freq" in k: core_config[k] = float(core_config[k]) if k == "sdram_module":