diff --git a/litedram/frontend/bist.py b/litedram/frontend/bist.py index bb7b9b6..e595da7 100644 --- a/litedram/frontend/bist.py +++ b/litedram/frontend/bist.py @@ -42,7 +42,7 @@ class Counter(Module): class _LiteDRAMBISTGenerator(Module): def __init__(self, dram_port, random): - self.shoot = Signal() + self.start = Signal() self.done = Signal() self.base = Signal(dram_port.aw) self.length = Signal(dram_port.aw) @@ -56,13 +56,13 @@ class _LiteDRAMBISTGenerator(Module): else: self.submodules.gen = gen = Counter(dram_port.dw) - self.shooted = shooted = Signal() + self.started = started = Signal() enable = Signal() counter = Signal(dram_port.aw) - self.comb += enable.eq(shooted & (counter != (self.length - 1))) + self.comb += enable.eq(started & (counter != (self.length - 1))) self.sync += [ - If(self.shoot, - shooted.eq(1), + If(self.start, + started.eq(1), counter.eq(0) ).Elif(gen.ce, counter.eq(counter + 1) @@ -75,14 +75,14 @@ class _LiteDRAMBISTGenerator(Module): dma.sink.data.eq(gen.o), gen.ce.eq(enable & dma.sink.ready), - self.done.eq(~enable & shooted) + self.done.eq(~enable & started) ] class LiteDRAMBISTGenerator(Module, AutoCSR): def __init__(self, dram_port, random=True): self.reset = CSR() - self.shoot = CSR() + self.start = CSR() self.done = CSRStatus() self.base = CSRStorage(dram_port.aw) self.length = CSRStorage(dram_port.aw) @@ -95,9 +95,9 @@ class LiteDRAMBISTGenerator(Module, AutoCSR): self.submodules.core = ClockDomainsRenamer(cd)(core) reset_sync = BusSynchronizer(1, "sys", cd) - shoot_sync = PulseSynchronizer("sys", cd) + start_sync = PulseSynchronizer("sys", cd) done_sync = BusSynchronizer(1, cd, "sys") - self.submodules += reset_sync, shoot_sync, done_sync + self.submodules += reset_sync, start_sync, done_sync base_sync = BusSynchronizer(dram_port.aw, "sys", cd) length_sync = BusSynchronizer(dram_port.aw, "sys", cd) @@ -107,8 +107,8 @@ class LiteDRAMBISTGenerator(Module, AutoCSR): reset_sync.i.eq(self.reset.re), core.reset.eq(reset_sync.o), - shoot_sync.i.eq(self.shoot.re), - core.shoot.eq(shoot_sync.o), + start_sync.i.eq(self.start.re), + core.start.eq(start_sync.o), done_sync.i.eq(core.done), self.done.status.eq(done_sync.o), @@ -123,7 +123,7 @@ class LiteDRAMBISTGenerator(Module, AutoCSR): class _LiteDRAMBISTChecker(Module, AutoCSR): def __init__(self, dram_port, random): - self.shoot = Signal() + self.start = Signal() self.done = Signal() self.base = Signal(dram_port.aw) self.length = Signal(dram_port.aw) @@ -138,21 +138,21 @@ class _LiteDRAMBISTChecker(Module, AutoCSR): else: self.submodules.gen = gen = Counter(dram_port.dw) - self.shooted = shooted = Signal() + self.started = started = Signal() address_counter = Signal(dram_port.aw) address_counter_ce = Signal() data_counter = Signal(dram_port.aw) data_counter_ce = Signal() self.sync += [ - If(self.shoot, - shooted.eq(1) + If(self.start, + started.eq(1) ), - If(self.shoot, + If(self.start, address_counter.eq(0) ).Elif(address_counter_ce, address_counter.eq(address_counter + 1) ), - If(self.shoot, + If(self.start, data_counter.eq(0), ).Elif(data_counter_ce, data_counter.eq(data_counter + 1) @@ -160,7 +160,7 @@ class _LiteDRAMBISTChecker(Module, AutoCSR): ] address_enable = Signal() - self.comb += address_enable.eq(shooted & (address_counter != (self.length - 1))) + self.comb += address_enable.eq(started & (address_counter != (self.length - 1))) self.comb += [ dma.sink.valid.eq(address_enable), @@ -169,7 +169,7 @@ class _LiteDRAMBISTChecker(Module, AutoCSR): ] data_enable = Signal() - self.comb += data_enable.eq(shooted & (data_counter != (self.length - 1))) + self.comb += data_enable.eq(started & (data_counter != (self.length - 1))) self.comb += [ gen.ce.eq(dma.source.valid), @@ -184,13 +184,13 @@ class _LiteDRAMBISTChecker(Module, AutoCSR): ] self.comb += data_counter_ce.eq(dma.source.valid) - self.comb += self.done.eq(~data_enable & ~address_enable & shooted) + self.comb += self.done.eq(~data_enable & ~address_enable & started) class LiteDRAMBISTChecker(Module, AutoCSR): def __init__(self, dram_port, random=True): self.reset = CSR() - self.shoot = CSR() + self.start = CSR() self.done = CSRStatus() self.base = CSRStorage(dram_port.aw) self.length = CSRStorage(dram_port.aw) @@ -204,9 +204,9 @@ class LiteDRAMBISTChecker(Module, AutoCSR): self.submodules.core = ClockDomainsRenamer(cd)(core) reset_sync = BusSynchronizer(1, "sys", cd) - shoot_sync = PulseSynchronizer("sys", cd) + start_sync = PulseSynchronizer("sys", cd) done_sync = BusSynchronizer(1, cd, "sys") - self.submodules += reset_sync, shoot_sync, done_sync + self.submodules += reset_sync, start_sync, done_sync base_sync = BusSynchronizer(dram_port.aw, "sys", cd) length_sync = BusSynchronizer(dram_port.aw, "sys", cd) @@ -217,8 +217,8 @@ class LiteDRAMBISTChecker(Module, AutoCSR): reset_sync.i.eq(self.reset.re), core.reset.eq(reset_sync.o), - shoot_sync.i.eq(self.shoot.re), - core.shoot.eq(shoot_sync.o), + start_sync.i.eq(self.start.re), + core.start.eq(start_sync.o), done_sync.i.eq(core.done), self.done.status.eq(done_sync.o), diff --git a/test/bist_async_tb.py b/test/bist_async_tb.py index f721ed6..699a6ba 100755 --- a/test/bist_async_tb.py +++ b/test/bist_async_tb.py @@ -81,9 +81,9 @@ def main_generator(dut): yield dut.generator.length.storage.eq(16) for i in range(32): yield - yield dut.generator.shoot.re.eq(1) + yield dut.generator.start.re.eq(1) yield - yield dut.generator.shoot.re.eq(0) + yield dut.generator.start.re.eq(0) for i in range(32): yield while((yield dut.generator.done.status) == 0): @@ -93,9 +93,9 @@ def main_generator(dut): yield dut.checker.length.storage.eq(16) for i in range(32): yield - yield dut.checker.shoot.re.eq(1) + yield dut.checker.start.re.eq(1) yield - yield dut.checker.shoot.re.eq(0) + yield dut.checker.start.re.eq(0) for i in range(32): yield while((yield dut.checker.done.status) == 0): diff --git a/test/bist_tb.py b/test/bist_tb.py index acad27a..f4fe618 100755 --- a/test/bist_tb.py +++ b/test/bist_tb.py @@ -39,8 +39,8 @@ def togglereset(module): yield # Check some initial conditions are correct after reset. - shooted = yield module.core.shooted - assert shooted == 0, shooted + started = yield module.core.started + assert started == 0, started done = yield module.done.status assert not done, done @@ -59,9 +59,9 @@ def main_generator(dut, mem): yield dut.generator.length.storage.eq(64) for i in range(8): yield - yield dut.generator.shoot.re.eq(1) + yield dut.generator.start.re.eq(1) yield - yield dut.generator.shoot.re.eq(0) + yield dut.generator.start.re.eq(0) for i in range(8): yield while((yield dut.generator.done.status) == 0): @@ -78,9 +78,9 @@ def main_generator(dut, mem): yield dut.checker.length.storage.eq(64) for i in range(8): yield - yield dut.checker.shoot.re.eq(1) + yield dut.checker.start.re.eq(1) yield - yield dut.checker.shoot.re.eq(0) + yield dut.checker.start.re.eq(0) for i in range(8): yield while((yield dut.checker.done.status) == 0): @@ -105,9 +105,9 @@ def main_generator(dut, mem): yield dut.checker.length.storage.eq(64) for i in range(8): yield - yield dut.checker.shoot.re.eq(1) + yield dut.checker.start.re.eq(1) yield - yield dut.checker.shoot.re.eq(0) + yield dut.checker.start.re.eq(0) for i in range(8): yield while((yield dut.checker.done.status) == 0):