From dc16d971ad515a5ea74df6c648185091efc96285 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 22 Jan 2020 16:31:13 +0100
Subject: [PATCH] modules: add M12L16161A

---
 litedram/modules.py | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/litedram/modules.py b/litedram/modules.py
index e58efa6..60b6ed2 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -210,6 +210,16 @@ class M12L64322A(SDRAMModule):
     technology_timings = _TechnologyTimings(tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
     speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)}
 
+class M12L16161A(SDRAMModule):
+    memtype = "SDR"
+    # geometry
+    nbanks = 2
+    nrows  = 2048
+    ncols  = 256
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)}
+
 # DDR ----------------------------------------------------------------------------------------------
 
 class MT46V32M16(SDRAMModule):
@@ -290,7 +300,6 @@ class P3R1GE4JGF(SDRAMModule):
     technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(None, 7.5), tCCD=(2, None), tRRD=None)
     speedgrade_timings = {"default": _SpeedgradeTimings(tRP=12.5, tRCD=12.5, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)}
 
-
 # DDR3 (Chips) -------------------------------------------------------------------------------------
 
 class MT41K64M16(SDRAMModule):