From dec537842200e9ec6ec37349d38bd4d856f9c003 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 13 Jul 2018 15:03:04 +0200
Subject: [PATCH] core/bankmachine: add CAS to CAS support (tCCD)

---
 litedram/common.py           |  3 ++-
 litedram/core/bankmachine.py | 47 ++++++++++++++++++++++++------------
 litedram/modules.py          |  6 ++++-
 3 files changed, 39 insertions(+), 17 deletions(-)

diff --git a/litedram/common.py b/litedram/common.py
index 65fda07..58773a9 100644
--- a/litedram/common.py
+++ b/litedram/common.py
@@ -31,7 +31,7 @@ class GeomSettings:
 
 
 class TimingSettings:
-    def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC, tFAW):
+    def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC, tFAW, tCCD):
         self.tRP = tRP
         self.tRCD = tRCD
         self.tWR = tWR
@@ -39,6 +39,7 @@ class TimingSettings:
         self.tREFI = tREFI
         self.tRFC = tRFC
         self.tFAW = tFAW
+        self.tCCD = tCCD
 
 
 def cmd_layout(aw):
diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py
index 253a44d..10651cf 100644
--- a/litedram/core/bankmachine.py
+++ b/litedram/core/bankmachine.py
@@ -94,6 +94,20 @@ class BankMachine(Module):
                 activate_count = next_activate_count
             self.comb += If(activate_count >=4, activate_allowed.eq(0))
 
+        # CAS to CAS
+        cas = Signal()
+        cas_allowed = Signal(reset=1)
+        tccd =  settings.timing.tCCD
+        if tccd is not None:
+            cas_count = Signal(max=tccd)
+            self.sync += \
+                If(cas,
+                    cas_count.eq(tccd-1)
+                ).Elif(~cas_allowed,
+                    cas_count.eq(cas_count-1)
+                )
+            self.comb += cas_allowed.eq(cas_count == 0)
+
         # Address generation
         sel_row_adr = Signal()
         self.comb += [
@@ -120,23 +134,26 @@ class BankMachine(Module):
             ).Elif(cmd_buffer1.source.valid,
                 If(has_openrow,
                     If(hit,
-                        # Note: write-to-read specification is enforced by
-                        # multiplexer
-                        cmd.valid.eq(1),
-                        If(cmd_buffer1.source.we,
-                            req.wdata_ready.eq(cmd.ready),
-                            cmd.is_write.eq(1),
-                            cmd.we.eq(1),
+                        If(cas_allowed,
+                            cas.eq(1),
+                            # Note: write-to-read specification is enforced by
+                            # multiplexer
+                            cmd.valid.eq(1),
+                            If(cmd_buffer1.source.we,
+                                req.wdata_ready.eq(cmd.ready),
+                                cmd.is_write.eq(1),
+                                cmd.we.eq(1),
+                            ).Else(
+                                req.rdata_valid.eq(cmd.ready),
+                                cmd.is_read.eq(1)
+                            ),
+                            cmd.cas.eq(1),
+                            If(cmd.ready & auto_precharge,
+                                NextState("AUTOPRECHARGE")
+                            )
                         ).Else(
-                            req.rdata_valid.eq(cmd.ready),
-                            cmd.is_read.eq(1)
-                        ),
-                        cmd.cas.eq(1),
-                        If(cmd.ready & auto_precharge,
-                            NextState("AUTOPRECHARGE")
+                            NextState("PRECHARGE")
                         )
-                    ).Else(
-                        NextState("PRECHARGE")
                     )
                 ).Else(
                     If(activate_allowed,
diff --git a/litedram/modules.py b/litedram/modules.py
index e51b5b2..ccb86f3 100644
--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -32,7 +32,8 @@ class SDRAMModule:
             tREFI=self.ns_to_cycles(self.get("tREFI"), False),
             tRFC=self.ns_to_cycles(self.get("tRFC")),
             tWTR=self.ck_ns_to_cycles(*self.get("tWTR")),
-            tFAW=None if self.get("tFAW") is None else self.ck_ns_to_cycles(*self.get("tFAW"))
+            tFAW=None if self.get("tFAW") is None else self.ck_ns_to_cycles(*self.get("tFAW")),
+            tCCD=None if self.get("tCCD") is None else self.ck_ns_to_cycles(*self.get("tCCD")),
         )
 
     def get(self, name):
@@ -228,6 +229,7 @@ class MT41J128M16(SDRAMModule):
     # speedgrade invariant timings
     tREFI = 64e6/8192
     tWTR  = (4, 7.5)
+    tCCD  = (4, None)
     # speedgrade related timings
     # DDR3-1066
     tRP_1066  = 13.1
@@ -283,6 +285,7 @@ class MT8JTF12864(SDRAMModule):
     # speedgrade invariant timings
     tREFI = 64e6/8192
     tWTR  = (4, 7.5)
+    tCCD  = (4, None)
     # speedgrade related timings
     # DDR3-1066
     tRP_1066  = 15
@@ -313,6 +316,7 @@ class MT18KSF1G72HZ(SDRAMModule):
     # speedgrade invariant timings
     tREFI = 64e6/8192
     tWTR = (4, 7.5)
+    tCCD  = (4, None)
     # DDR3-1066
     tRP_1066  = 15
     tRCD_1066 = 15