From df5f555842aa2b02cbc7ca2d5ad9a02bd8cec52e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 12 Mar 2021 10:25:11 +0100 Subject: [PATCH] bench: Update with recent changes. --- bench/arty.py | 4 +--- bench/genesys2.py | 4 +--- bench/kc705.py | 4 +--- bench/kcu105.py | 7 ++----- bench/xcu1525.py | 7 ++----- 5 files changed, 7 insertions(+), 19 deletions(-) diff --git a/bench/arty.py b/bench/arty.py index 21b9333..eac4018 100755 --- a/bench/arty.py +++ b/bench/arty.py @@ -74,7 +74,6 @@ class BenchSoC(SoCCore): ident_version = True, integrated_rom_size = 0x10000, integrated_rom_mode = "rw", - csr_data_width = 32, uart_name = uart) # CRG -------------------------------------------------------------------------------------- @@ -91,8 +90,7 @@ class BenchSoC(SoCCore): phy = self.ddrphy, module = MT41K128M16(sys_clk_freq, "1:4"), origin = self.mem_map["main_ram"], - with_bist = with_bist, - ) + with_bist = with_bist) # UARTBone --------------------------------------------------------------------------------- if uart != "serial": diff --git a/bench/genesys2.py b/bench/genesys2.py index a617cea..9b0a3c0 100755 --- a/bench/genesys2.py +++ b/bench/genesys2.py @@ -68,7 +68,6 @@ class BenchSoC(SoCCore): ident_version = True, integrated_rom_size = 0x10000, integrated_rom_mode = "rw", - csr_data_width = 32, uart_name = uart) # CRG -------------------------------------------------------------------------------------- @@ -85,8 +84,7 @@ class BenchSoC(SoCCore): phy = self.ddrphy, module = MT41J256M16(sys_clk_freq, "1:4"), origin = self.mem_map["main_ram"], - with_bist = with_bist, - ) + with_bist = with_bist) # UARTBone --------------------------------------------------------------------------------- if uart != "serial": diff --git a/bench/kc705.py b/bench/kc705.py index 4dcd908..f59854e 100755 --- a/bench/kc705.py +++ b/bench/kc705.py @@ -68,7 +68,6 @@ class BenchSoC(SoCCore): ident_version = True, integrated_rom_size = 0x10000, integrated_rom_mode = "rw", - csr_data_width = 32, uart_name = uart) # CRG -------------------------------------------------------------------------------------- @@ -85,8 +84,7 @@ class BenchSoC(SoCCore): phy = self.ddrphy, module = MT8JTF12864(sys_clk_freq, "1:4"), origin = self.mem_map["main_ram"], - with_bist = with_bist, - ) + with_bist = with_bist) # UARTBone --------------------------------------------------------------------------------- if uart != "serial": diff --git a/bench/kcu105.py b/bench/kcu105.py index 020f6c5..a27d763 100755 --- a/bench/kcu105.py +++ b/bench/kcu105.py @@ -43,7 +43,7 @@ class _CRG(Module, AutoCSR): self.comb += main_pll.reset.eq(platform.request("cpu_reset")) main_pll.register_clkin(platform.request("clk125"), 125e6) main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq) - main_pll.create_clkout(self.cd_idelay, 200e6, with_reset=False) + main_pll.create_clkout(self.cd_idelay, 200e6) main_pll.create_clkout(self.cd_uart, 100e6) main_pll.create_clkout(self.cd_eth, 200e6) main_pll.expose_drp() @@ -65,7 +65,6 @@ class _CRG(Module, AutoCSR): i_I = self.cd_pll4x.clk, o_O = self.cd_sys4x.clk, ), - AsyncResetSynchronizer(self.cd_idelay, ~pll.locked), ] self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys) @@ -87,7 +86,6 @@ class BenchSoC(SoCCore): ident_version = True, integrated_rom_size = 0x10000, integrated_rom_mode = "rw", - csr_data_width = 32, uart_name = uart) # CRG -------------------------------------------------------------------------------------- @@ -105,8 +103,7 @@ class BenchSoC(SoCCore): module = EDY4016A(sys_clk_freq, "1:4"), origin = self.mem_map["main_ram"], size = 0x40000000, - with_bist = with_bist, - ) + with_bist = with_bist) # UARTBone --------------------------------------------------------------------------------- if uart != "serial": diff --git a/bench/xcu1525.py b/bench/xcu1525.py index 7660296..9df3eab 100755 --- a/bench/xcu1525.py +++ b/bench/xcu1525.py @@ -40,7 +40,7 @@ class _CRG(Module, AutoCSR): self.submodules.main_pll = main_pll = USPMMCM(speedgrade=-2) main_pll.register_clkin(platform.request("clk300", channel), 300e6) main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq) - main_pll.create_clkout(self.cd_idelay, 500e6, with_reset=False) + main_pll.create_clkout(self.cd_idelay, 500e6) main_pll.create_clkout(self.cd_uart, 100e6) main_pll.expose_drp() @@ -61,7 +61,6 @@ class _CRG(Module, AutoCSR): i_I = self.cd_pll4x.clk, o_O = self.cd_sys4x.clk, ), - AsyncResetSynchronizer(self.cd_idelay, ~pll.locked), ] self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys) @@ -83,7 +82,6 @@ class BenchSoC(SoCCore): ident_version = True, integrated_rom_size = 0x10000, integrated_rom_mode = "rw", - csr_data_width = 32, uart_name = uart) # CRG -------------------------------------------------------------------------------------- @@ -101,8 +99,7 @@ class BenchSoC(SoCCore): module = MT40A512M8(sys_clk_freq, "1:4"), origin = self.mem_map["main_ram"], size = 0x40000000, - with_bist = with_bist, - ) + with_bist = with_bist) # Workaround for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions. platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]")