From e07198ac570344b576002adae1b3cc3529aa42b3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?J=C4=99drzej=20Boczar?= <jboczar@antmicro.com>
Date: Wed, 24 Mar 2021 13:08:51 +0100
Subject: [PATCH] lpddr4/utils: simplify ConstBitSlip

---
 litedram/phy/lpddr4/utils.py | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/litedram/phy/lpddr4/utils.py b/litedram/phy/lpddr4/utils.py
index 68ef46a..a08cd18 100644
--- a/litedram/phy/lpddr4/utils.py
+++ b/litedram/phy/lpddr4/utils.py
@@ -42,10 +42,7 @@ class ConstBitSlip(Module):
 
         self.r = r = Signal((cycles+1)*dw, reset_less=True)
         self.sync += r.eq(Cat(r[dw:], self.i))
-        cases = {}
-        for i in range(cycles*dw):
-            cases[i] = self.o.eq(r[i+1:dw+i+1])
-        self.comb += Case(slp, cases)
+        self.comb += self.o.eq(r[slp+1:dw+slp+1])
 
 # TODO: rewrite DQSPattern in litedram/common.py to support different data widths
 class DQSPattern(Module):