From e0cf7d579e6c0d08423753a69b97ab7264c00112 Mon Sep 17 00:00:00 2001
From: Anton Blanchard <anton@ozlabs.org>
Date: Sat, 2 Oct 2021 13:26:26 +1000
Subject: [PATCH] phy/ecp5ddrphy: set rtt_nom/rtt_wr/ron from YAML config

---
 litedram/gen.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/litedram/gen.py b/litedram/gen.py
index d1f131c..0a7016a 100755
--- a/litedram/gen.py
+++ b/litedram/gen.py
@@ -567,6 +567,10 @@ class LiteDRAMCore(SoCCore):
             self.submodules.ddrphy = sdram_phy = core_config["sdram_phy"](
                 pads         = platform.request("ddram"),
                 sys_clk_freq = sys_clk_freq)
+            self.ddrphy.settings.add_electrical_settings(
+                rtt_nom = core_config["rtt_nom"],
+                rtt_wr  = core_config["rtt_wr"],
+                ron     = core_config["ron"])
             self.comb += crg.stop.eq(self.ddrphy.init.stop)
             self.comb += crg.reset.eq(self.ddrphy.init.reset)