diff --git a/litedram/gen.py b/litedram/gen.py
index 65bcfe5..2535581 100755
--- a/litedram/gen.py
+++ b/litedram/gen.py
@@ -567,7 +567,12 @@ class LiteDRAMCore(SoCCore):
             assert core_config["memtype"] in ["DDR3"]
             self.submodules.ddrphy = sdram_phy = core_config["sdram_phy"](
                 pads         = platform.request("ddram"),
-                sys_clk_freq = sys_clk_freq)
+                sys_clk_freq = sys_clk_freq,
+                cmd_delay    = core_config["cmd_delay"])
+            self.ddrphy.settings.add_electrical_settings(
+                rtt_nom = core_config["rtt_nom"],
+                rtt_wr  = core_config["rtt_wr"],
+                ron     = core_config["ron"])
             self.comb += crg.stop.eq(self.ddrphy.init.stop)
             self.comb += crg.reset.eq(self.ddrphy.init.reset)