From e0cf7d579e6c0d08423753a69b97ab7264c00112 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sat, 2 Oct 2021 13:26:26 +1000 Subject: [PATCH 1/2] phy/ecp5ddrphy: set rtt_nom/rtt_wr/ron from YAML config --- litedram/gen.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/litedram/gen.py b/litedram/gen.py index d1f131c..0a7016a 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -567,6 +567,10 @@ class LiteDRAMCore(SoCCore): self.submodules.ddrphy = sdram_phy = core_config["sdram_phy"]( pads = platform.request("ddram"), sys_clk_freq = sys_clk_freq) + self.ddrphy.settings.add_electrical_settings( + rtt_nom = core_config["rtt_nom"], + rtt_wr = core_config["rtt_wr"], + ron = core_config["ron"]) self.comb += crg.stop.eq(self.ddrphy.init.stop) self.comb += crg.reset.eq(self.ddrphy.init.reset) From 99f53fcd1f472b4b0734c1d17f49f6f92e8893a2 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sun, 3 Oct 2021 19:03:22 +1100 Subject: [PATCH 2/2] phy/ecp5ddrphy: set cmd_delay from YAML config --- litedram/gen.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litedram/gen.py b/litedram/gen.py index 0a7016a..69e6913 100755 --- a/litedram/gen.py +++ b/litedram/gen.py @@ -566,7 +566,8 @@ class LiteDRAMCore(SoCCore): assert core_config["memtype"] in ["DDR3"] self.submodules.ddrphy = sdram_phy = core_config["sdram_phy"]( pads = platform.request("ddram"), - sys_clk_freq = sys_clk_freq) + sys_clk_freq = sys_clk_freq, + cmd_delay = core_config["cmd_delay"]) self.ddrphy.settings.add_electrical_settings( rtt_nom = core_config["rtt_nom"], rtt_wr = core_config["rtt_wr"],