From e1598ceee8fbfa9969a223d6f547c5cf1d38b92f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Sep 2018 09:34:10 +0200 Subject: [PATCH] phy/s7ddrphy: fix BL8 assert --- litedram/phy/s7ddrphy.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litedram/phy/s7ddrphy.py b/litedram/phy/s7ddrphy.py index a98e2c3..bc6625b 100644 --- a/litedram/phy/s7ddrphy.py +++ b/litedram/phy/s7ddrphy.py @@ -43,7 +43,7 @@ def get_sys_phases(nphases, sys_latency, cas_latency): class S7DDRPHY(Module, AutoCSR): def __init__(self, pads, with_odelay, memtype="DDR3", nphases=4, sys_clk_freq=100e6, iodelay_clk_freq=200e6): - assert (not memtype == "DDR3" and nphases == 2) # FIXME: Needs BL8 support for nphases=2 + assert not (memtype == "DDR3" and nphases == 2) # FIXME: Needs BL8 support for nphases=2 tck = 2/(2*nphases*sys_clk_freq) addressbits = len(pads.a) bankbits = len(pads.ba)