diff --git a/test/common.py b/test/common.py
index 5f7c575..e8f0f2d 100644
--- a/test/common.py
+++ b/test/common.py
@@ -1,5 +1,21 @@
 from litex.gen import *
 
+
+def seed_to_data(seed, random=True, nbits=32):
+    if nbits == 32:
+        if random:
+            return (seed * 0x31415979 + 1) & 0xffffffff
+        else:
+            return seed
+    else:
+        assert nbits%32 == 0
+        data = 0
+        for i in range(nbits//32):
+            data = data << 32
+            data |= seed_to_data(seed*nbits//32 + i, random, 32)
+        return data
+
+
 class DRAMMemory:
     def __init__(self, width, depth, init=[]):
         self.width = width
diff --git a/test/downconverter_tb.py b/test/downconverter_tb.py
index d8d7900..f3dbace 100755
--- a/test/downconverter_tb.py
+++ b/test/downconverter_tb.py
@@ -3,11 +3,12 @@
 from litex.gen import *
 
 from litex.soc.interconnect.stream import *
+from litex.soc.interconnect.stream_sim import check
 
 from litedram.common import LiteDRAMPort
 from litedram.frontend.adaptation import LiteDRAMPortConverter
 
-from test.common import DRAMMemory
+from test.common import *
 
 class TB(Module):
     def __init__(self):
@@ -17,22 +18,33 @@ class TB(Module):
                                                           self.crossbar_port)
         self.memory = DRAMMemory(32, 128)
 
-def main_generator(dut):
-    for i in range(8):
+
+write_data = [seed_to_data(i, nbits=64) for i in range(8)]
+read_data = []
+
+@passive
+def read_generator(dut):
+    yield dut.user_port.rdata.ready.eq(1)
+    while True:
+        if (yield dut.user_port.rdata.valid):
+            read_data.append((yield dut.user_port.rdata.data))
         yield
+
+def main_generator(dut):
     # write
     for i in range(8):
         yield dut.user_port.cmd.valid.eq(1)
         yield dut.user_port.cmd.we.eq(1)
         yield dut.user_port.cmd.adr.eq(i)
         yield dut.user_port.wdata.valid.eq(1)
-        yield dut.user_port.wdata.data.eq(0x0123456789abcdef)
+        yield dut.user_port.wdata.data.eq(write_data[i])
         yield
         while (yield dut.user_port.cmd.ready) == 0:
             yield
         while (yield dut.user_port.wdata.ready) == 0:
             yield
         yield
+
     # read
     yield dut.user_port.rdata.ready.eq(1)
     for i in range(8):
@@ -45,12 +57,21 @@ def main_generator(dut):
         yield dut.user_port.cmd.valid.eq(0)
         yield
 
+    # delay
+    for i in range(32):
+        yield
+
+    # check
+    s, l, e = check(write_data, read_data)
+    print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
+
 if __name__ == "__main__":
     tb = TB()
     generators = {
         "sys" :   [main_generator(tb),
+                   read_generator(tb),
                    tb.memory.write_generator(tb.crossbar_port),
                    tb.memory.read_generator(tb.crossbar_port)]
     }
     clocks = {"sys": 10}
-    run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
+    run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
\ No newline at end of file
diff --git a/test/upconverter_tb.py b/test/upconverter_tb.py
index 1f7ac55..bf6c6e9 100755
--- a/test/upconverter_tb.py
+++ b/test/upconverter_tb.py
@@ -3,11 +3,12 @@
 from litex.gen import *
 
 from litex.soc.interconnect.stream import *
+from litex.soc.interconnect.stream_sim import check
 
 from litedram.common import LiteDRAMPort
 from litedram.frontend.adaptation import LiteDRAMPortConverter
 
-from test.common import DRAMMemory
+from test.common import *
 
 class TB(Module):
     def __init__(self):
@@ -17,9 +18,18 @@ class TB(Module):
                                                           self.crossbar_port)
         self.memory = DRAMMemory(64, 128)
 
-def main_generator(dut):
-    for i in range(8):
+write_data = [seed_to_data(i, nbits=32) for i in range(8)]
+read_data = []
+
+@passive
+def read_generator(dut):
+    yield dut.user_port.rdata.ready.eq(1)
+    while True:
+        if (yield dut.user_port.rdata.valid):
+            read_data.append((yield dut.user_port.rdata.data))
         yield
+
+def main_generator(dut):
     # write
     for i in range(8):
         yield dut.user_port.cmd.valid.eq(1)
@@ -31,18 +41,15 @@ def main_generator(dut):
         yield dut.user_port.cmd.valid.eq(0)
         yield
         yield dut.user_port.wdata.valid.eq(1)
-        if i%2:
-            yield dut.user_port.wdata.data.eq(0x01234567)
-        else:
-            yield dut.user_port.wdata.data.eq(0x89abcdef)        
+        yield dut.user_port.wdata.data.eq(write_data[i])   
         yield
         while (yield dut.user_port.wdata.ready) == 0:
             yield
         yield dut.user_port.wdata.valid.eq(0)
         yield
+
     # read
     for i in range(8):
-        yield dut.user_port.rdata.ready.eq(1)
         for j in range(2):
             yield dut.user_port.cmd.valid.eq(1)
             yield dut.user_port.cmd.we.eq(0)
@@ -53,10 +60,20 @@ def main_generator(dut):
             yield dut.user_port.cmd.valid.eq(0)
             yield
 
+    # delay
+    for i in range(32):
+        yield
+
+    # check
+    s, l, e = check(write_data, read_data)
+    print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
+
+
 if __name__ == "__main__":
     tb = TB()
     generators = {
         "sys" :   [main_generator(tb),
+                   read_generator(tb),
                    tb.memory.write_generator(tb.crossbar_port),
                    tb.memory.read_generator(tb.crossbar_port)]
     }