From e6a99d9cbc65c4b304b134228617fd2de58f89e8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 8 Mar 2018 13:06:46 +0100 Subject: [PATCH] phy/kusddrphy: revert dqs preamble/postamble since not working for continous transfer, will need a proper implementation --- litedram/phy/kusddrphy.py | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/litedram/phy/kusddrphy.py b/litedram/phy/kusddrphy.py index 9a89ea1..ba85c62 100644 --- a/litedram/phy/kusddrphy.py +++ b/litedram/phy/kusddrphy.py @@ -117,8 +117,6 @@ class KUSDDRPHY(Module, AutoCSR): # DQS and DM oe_dqs = Signal() - oe_dqs_preamble = Signal() - oe_dqs_postamble = Signal() dqs_serdes_pattern = Signal(8) self.comb += \ If(self._wlevel_en.storage, @@ -128,13 +126,7 @@ class KUSDDRPHY(Module, AutoCSR): dqs_serdes_pattern.eq(0b00000000) ) ).Else( - If(oe_dqs_preamble, - dqs_serdes_pattern.eq(0b01000000) - ).Elif(oe_dqs_postamble, - dqs_serdes_pattern.eq(0b00000001) - ).Else( - dqs_serdes_pattern.eq(0b01010101) - ) + dqs_serdes_pattern.eq(0b01010101) ) for i in range(databits//8): dm_o_nodelay = Signal() @@ -321,12 +313,9 @@ class KUSDDRPHY(Module, AutoCSR): wrphase = self.dfi.phases[self.settings.wrphase] self.sync += last_wrdata_en.eq(Cat(wrphase.wrdata_en, last_wrdata_en[:3])) self.comb += oe.eq(last_wrdata_en[1] | last_wrdata_en[2] | last_wrdata_en[3]) - self.sync += [ - oe_dqs_preamble.eq(last_wrdata_en[1]), - oe_dqs_postamble.eq(last_wrdata_en[3]), + self.sync += \ If(self._wlevel_en.storage, oe_dqs.eq(1), oe_dq.eq(0) ).Else( oe_dqs.eq(oe), oe_dq.eq(oe) ) - ]