diff --git a/litedram/common.py b/litedram/common.py index 7b423a5..9f717a8 100644 --- a/litedram/common.py +++ b/litedram/common.py @@ -40,21 +40,22 @@ class TimingSettings: def cmd_layout(aw): return [ - ("valid", 1, DIR_M_TO_S), - ("ready", 1, DIR_S_TO_M), - ("we", 1, DIR_M_TO_S), - ("adr", aw, DIR_M_TO_S), - ("dat_w_ack", 1, DIR_S_TO_M), - ("dat_r_ack", 1, DIR_S_TO_M), - ("lock", 1, DIR_S_TO_M) + ("valid", 1, DIR_M_TO_S), + ("ready", 1, DIR_S_TO_M), + ("we", 1, DIR_M_TO_S), + ("adr", aw, DIR_M_TO_S), + ("lock", 1, DIR_S_TO_M), + + ("wdata_ready", 1, DIR_S_TO_M), + ("rdata_valid", 1, DIR_S_TO_M) ] def data_layout(dw): return [ - ("dat_w", dw, DIR_M_TO_S), - ("dat_we", dw//8, DIR_M_TO_S), - ("dat_r", dw, DIR_S_TO_M) + ("wdata", dw, DIR_M_TO_S), + ("wdata_we", dw//8, DIR_M_TO_S), + ("rdata", dw, DIR_S_TO_M) ] diff --git a/litedram/core/bankmachine.py b/litedram/core/bankmachine.py index 57cacc6..c86b016 100644 --- a/litedram/core/bankmachine.py +++ b/litedram/core/bankmachine.py @@ -46,8 +46,8 @@ class BankMachine(Module): settings.cmd_buffer_depth) self.submodules += cmd_buffer self.comb += [ - req.connect(cmd_buffer.sink, omit=["dat_w_ack", "dat_r_ack", "lock"]), - cmd_buffer.source.ready.eq(req.dat_w_ack | req.dat_r_ack), + req.connect(cmd_buffer.sink, omit=["wdata_ready", "rdata_valid", "lock"]), + cmd_buffer.source.ready.eq(req.wdata_ready | req.rdata_valid), req.lock.eq(cmd_buffer.source.valid), ] @@ -98,11 +98,11 @@ class BankMachine(Module): # multiplexer cmd.valid.eq(1), If(cmd_buffer.source.we, - req.dat_w_ack.eq(cmd.ready), + req.wdata_ready.eq(cmd.ready), cmd.is_write.eq(1), cmd.we.eq(1), ).Else( - req.dat_r_ack.eq(cmd.ready), + req.rdata_valid.eq(cmd.ready), cmd.is_read.eq(1) ), cmd.cas.eq(1) diff --git a/litedram/core/multiplexer.py b/litedram/core/multiplexer.py index 461c015..8864421 100644 --- a/litedram/core/multiplexer.py +++ b/litedram/core/multiplexer.py @@ -169,9 +169,9 @@ class Multiplexer(Module, AutoCSR): all_wrdata = [p.wrdata for p in dfi.phases] all_wrdata_mask = [p.wrdata_mask for p in dfi.phases] self.comb += [ - interface.dat_r.eq(Cat(*all_rddata)), - Cat(*all_wrdata).eq(interface.dat_w), - Cat(*all_wrdata_mask).eq(~interface.dat_we) + interface.rdata.eq(Cat(*all_rddata)), + Cat(*all_wrdata).eq(interface.wdata), + Cat(*all_wrdata_mask).eq(~interface.wdata_we) ] def steerer_sel(steerer, r_w_n): diff --git a/litedram/frontend/bridge.py b/litedram/frontend/bridge.py index d2c10f2..7a20a56 100644 --- a/litedram/frontend/bridge.py +++ b/litedram/frontend/bridge.py @@ -25,14 +25,14 @@ class LiteDRAMWishboneBridge(Module): ) ) fsm.act("WRITE_DATA", - If(port.dat_w_ack, - port.dat_we.eq(wishbone.sel), + If(port.wdata_ready, + port.wdata_we.eq(wishbone.sel), wishbone.ack.eq(1), NextState("IDLE") ) ) fsm.act("READ_DATA", - If(port.dat_r_ack, + If(port.rdata_valid, wishbone.ack.eq(1), NextState("IDLE") ) @@ -41,8 +41,8 @@ class LiteDRAMWishboneBridge(Module): # Address / Datapath self.comb += [ port.adr.eq(wishbone.adr), - If(port.dat_w_ack, - port.dat_w.eq(wishbone.dat_w), + If(port.wdata_ready, + port.wdata.eq(wishbone.dat_w), ), - wishbone.dat_r.eq(port.dat_r) + wishbone.dat_r.eq(port.rdata) ] diff --git a/litedram/frontend/crossbar.py b/litedram/frontend/crossbar.py index 0ae6bb4..b435269 100644 --- a/litedram/frontend/crossbar.py +++ b/litedram/frontend/crossbar.py @@ -41,8 +41,8 @@ class LiteDRAMCrossbar(Module): controller = self.controller controller_selected = [1]*nmasters master_readys = [0]*nmasters - master_dat_w_acks = [0]*nmasters - master_dat_r_acks = [0]*nmasters + master_wdata_readys = [0]*nmasters + master_rdata_valids = [0]*nmasters rrs = [roundrobin.RoundRobin(nmasters, roundrobin.SP_CE) for n in range(self.nbanks)] self.submodules += rrs @@ -75,28 +75,28 @@ class LiteDRAMCrossbar(Module): ] master_readys = [master_ready | ((rr.grant == nm) & bank_selected[nm] & bank.ready) for nm, master_ready in enumerate(master_readys)] - master_dat_w_acks = [master_dat_w_ack | ((rr.grant == nm) & bank.dat_w_ack) - for nm, master_dat_w_ack in enumerate(master_dat_w_acks)] - master_dat_r_acks = [master_dat_r_ack | ((rr.grant == nm) & bank.dat_r_ack) - for nm, master_dat_r_ack in enumerate(master_dat_r_acks)] + master_wdata_readys = [master_wdata_ready | ((rr.grant == nm) & bank.wdata_ready) + for nm, master_wdata_ready in enumerate(master_wdata_readys)] + master_rdata_valids = [master_rdata_valid | ((rr.grant == nm) & bank.rdata_valid) + for nm, master_rdata_valid in enumerate(master_rdata_valids)] - for nm, master_dat_w_ack in enumerate(master_dat_w_acks): + for nm, master_wdata_ready in enumerate(master_wdata_readys): for i in range(self.write_latency): - new_master_dat_w_ack = Signal() - self.sync += new_master_dat_w_ack.eq(master_dat_w_ack) - master_dat_w_ack = new_master_dat_w_ack - master_dat_w_acks[nm] = master_dat_w_ack + new_master_wdata_ready = Signal() + self.sync += new_master_wdata_ready.eq(master_wdata_ready) + master_wdata_ready = new_master_wdata_ready + master_wdata_readys[nm] = master_wdata_ready - for nm, master_dat_r_ack in enumerate(master_dat_r_acks): + for nm, master_rdata_valid in enumerate(master_rdata_valids): for i in range(self.read_latency): - new_master_dat_r_ack = Signal() - self.sync += new_master_dat_r_ack.eq(master_dat_r_ack) - master_dat_r_ack = new_master_dat_r_ack - master_dat_r_acks[nm] = master_dat_r_ack + new_master_rdata_valid = Signal() + self.sync += new_master_rdata_valid.eq(master_rdata_valid) + master_rdata_valid = new_master_rdata_valid + master_rdata_valids[nm] = master_rdata_valid self.comb += [master.ready.eq(master_ready) for master, master_ready in zip(self.masters, master_readys)] - self.comb += [master.dat_w_ack.eq(master_dat_w_ack) for master, master_dat_w_ack in zip(self.masters, master_dat_w_acks)] - self.comb += [master.dat_r_ack.eq(master_dat_r_ack) for master, master_dat_r_ack in zip(self.masters, master_dat_r_acks)] + self.comb += [master.wdata_ready.eq(master_wdata_ready) for master, master_wdata_ready in zip(self.masters, master_wdata_readys)] + self.comb += [master.rdata_valid.eq(master_rdata_valid) for master, master_rdata_valid in zip(self.masters, master_rdata_valids)] # route data writes controller_selected_wl = controller_selected @@ -104,24 +104,24 @@ class LiteDRAMCrossbar(Module): n_controller_selected_wl = [Signal() for i in range(nmasters)] self.sync += [n.eq(o) for n, o in zip(n_controller_selected_wl, controller_selected_wl)] controller_selected_wl = n_controller_selected_wl - dat_w_maskselect = [] - dat_we_maskselect = [] + wdata_maskselect = [] + wdata_we_maskselect = [] for master, selected in zip(self.masters, controller_selected_wl): - o_dat_w = Signal(self.dw) - o_dat_we = Signal(self.dw//8) + o_wdata = Signal(self.dw) + o_wdata_we = Signal(self.dw//8) self.comb += If(selected, - o_dat_w.eq(master.dat_w), - o_dat_we.eq(master.dat_we) + o_wdata.eq(master.wdata), + o_wdata_we.eq(master.wdata_we) ) - dat_w_maskselect.append(o_dat_w) - dat_we_maskselect.append(o_dat_we) + wdata_maskselect.append(o_wdata) + wdata_we_maskselect.append(o_wdata_we) self.comb += [ - controller.dat_w.eq(reduce(or_, dat_w_maskselect)), - controller.dat_we.eq(reduce(or_, dat_we_maskselect)) + controller.wdata.eq(reduce(or_, wdata_maskselect)), + controller.wdata_we.eq(reduce(or_, wdata_we_maskselect)) ] # route data reads - self.comb += [master.dat_r.eq(self.controller.dat_r) for master in self.masters] + self.comb += [master.rdata.eq(self.controller.rdata) for master in self.masters] def split_master_addresses(self, bank_bits, rca_bits, cba_shift): m_ba = [] # bank address diff --git a/litedram/frontend/dma.py b/litedram/frontend/dma.py index d9eb47f..8b0267a 100644 --- a/litedram/frontend/dma.py +++ b/litedram/frontend/dma.py @@ -48,8 +48,8 @@ class LiteDRAMDMAReader(Module): self.submodules += fifo self.comb += [ - fifo.din.eq(port.dat_r), - fifo.we.eq(port.dat_r_ack), + fifo.din.eq(port.rdata), + fifo.we.eq(port.rdata_valid), source.valid.eq(fifo.readable), fifo.re.eq(source.ready), @@ -82,10 +82,10 @@ class LiteDRAMDMAWriter(Module): ] self.comb += [ - If(port.dat_w_ack, + If(port.wdata_ready, fifo.re.eq(1), - port.dat_we.eq(2**(port.dw//8)-1), - port.dat_w.eq(fifo.dout) + port.wdata_we.eq(2**(port.dw//8)-1), + port.wdata.eq(fifo.dout) ), self.busy.eq(fifo.readable) ] diff --git a/litedram/phy/model.py b/litedram/phy/model.py index bd8cbb3..291169a 100644 --- a/litedram/phy/model.py +++ b/litedram/phy/model.py @@ -49,11 +49,11 @@ class Bank(Module): self.comb += [ If(active, write_port.adr.eq(row*ncols | self.write_col), - write_port.dat_w.eq(self.write_data), + write_port.wdata.eq(self.write_data), write_port.we.eq(Replicate(self.write, data_width//8) & ~self.write_mask), If(self.read, read_port.adr.eq(row*ncols | self.read_col), - self.read_data.eq(read_port.dat_r) + self.read_data.eq(read_port.rdata) ) ) ]