diff --git a/litedram/frontend/axi.py b/litedram/frontend/axi.py
index a4b6522..22336c4 100644
--- a/litedram/frontend/axi.py
+++ b/litedram/frontend/axi.py
@@ -26,69 +26,6 @@ class LiteDRAMAXIPort(AXIInterface):
     pass
 
 
-class LiteDRAMAXIBurst2Beat(Module):
-    def __init__(self, ax_burst, ax_beat):
-
-        # # #
-
-        self.count = count = Signal(8)
-        size = Signal(8 + 4)
-        offset = Signal(8 + 4)
-
-        # convert burst size to bytes
-        cases = {}
-        cases["default"] = size.eq(1024)
-        for i in range(10):
-            cases[i] = size.eq(2**i)
-        self.comb += Case(ax_burst.size, cases)
-
-        # fsm
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
-        fsm.act("IDLE",
-            ax_beat.valid.eq(ax_burst.valid),
-            ax_beat.first.eq(1),
-            ax_beat.last.eq(ax_burst.len == 0),
-            ax_beat.addr.eq(ax_burst.addr),
-            ax_beat.id.eq(ax_burst.id),
-            If(ax_beat.valid & ax_beat.ready,
-                If(ax_burst.len != 0,
-                    NextState("BURST2BEAT")
-                ).Else(
-                    ax_burst.ready.eq(1)
-                )
-            ),
-            NextValue(count, 1),
-            NextValue(offset, size),
-        )
-        wrap_offset = Signal(8 + 4)
-        self.sync += wrap_offset.eq((ax_burst.len - 1)*size)
-        fsm.act("BURST2BEAT",
-            ax_beat.valid.eq(1),
-            ax_beat.first.eq(0),
-            ax_beat.last.eq(count == ax_burst.len),
-            If((ax_burst.burst == BURST_INCR) |
-               (ax_burst.burst == BURST_WRAP),
-                ax_beat.addr.eq(ax_burst.addr + offset)
-            ).Else(
-                ax_beat.addr.eq(ax_burst.addr)
-            ),
-            ax_beat.id.eq(ax_burst.id),
-            If(ax_beat.valid & ax_beat.ready,
-                If(ax_beat.last,
-                    ax_burst.ready.eq(1),
-                    NextState("IDLE")
-                ),
-                NextValue(count, count + 1),
-                NextValue(offset, offset + size),
-                If(ax_burst.burst == BURST_WRAP,
-                    If(offset == wrap_offset,
-                        NextValue(offset, 0)
-                    )
-                )
-            )
-        )
-
-
 class LiteDRAMAXI2NativeW(Module):
     def __init__(self, axi, port, buffer_depth):
         self.cmd_request = Signal()
@@ -103,7 +40,7 @@ class LiteDRAMAXI2NativeW(Module):
         self.submodules += aw_buffer
         self.comb += axi.aw.connect(aw_buffer.sink)
         aw = stream.Endpoint(ax_description(axi.address_width, axi.id_width))
-        aw_burst2beat = LiteDRAMAXIBurst2Beat(aw_buffer.source, aw)
+        aw_burst2beat = AXIBurst2Beat(aw_buffer.source, aw)
         self.submodules.aw_burst2beat = aw_burst2beat
 
         # Write Buffer
@@ -171,7 +108,7 @@ class LiteDRAMAXI2NativeR(Module):
         self.submodules += ar_buffer
         self.comb += axi.ar.connect(ar_buffer.sink)
         ar = stream.Endpoint(ax_description(axi.address_width, axi.id_width))
-        ar_burst2beat = LiteDRAMAXIBurst2Beat(ar_buffer.source, ar)
+        ar_burst2beat = AXIBurst2Beat(ar_buffer.source, ar)
         self.submodules.ar_burst2beat = ar_burst2beat
 
         # Read buffer
diff --git a/test/test_axi.py b/test/test_axi.py
index a7a6b7e..f5ef89b 100755
--- a/test/test_axi.py
+++ b/test/test_axi.py
@@ -53,65 +53,6 @@ class Read(Access):
 
 
 class TestAXI(unittest.TestCase):
-    def test_burst2beat(self):
-        def bursts_generator(ax, bursts, valid_rand=50):
-            prng = random.Random(42)
-            for burst in bursts:
-                yield ax.valid.eq(1)
-                yield ax.addr.eq(burst.addr)
-                yield ax.burst.eq(burst.type)
-                yield ax.len.eq(burst.len)
-                yield ax.size.eq(burst.size)
-                while (yield ax.ready) == 0:
-                    yield
-                yield ax.valid.eq(0)
-                while prng.randrange(100) < valid_rand:
-                    yield
-                yield
-
-        @passive
-        def beats_checker(ax, beats, ready_rand=50):
-            self.errors = 0
-            yield ax.ready.eq(0)
-            prng = random.Random(42)
-            for beat in beats:
-                while ((yield ax.valid) and (yield ax.ready)) == 0:
-                    if prng.randrange(100) > ready_rand:
-                        yield ax.ready.eq(1)
-                    else:
-                        yield ax.ready.eq(0)
-                    yield
-                ax_addr = (yield ax.addr)
-                if ax_addr != beat.addr:
-                    self.errors += 1
-                yield
-
-        # dut
-        ax_burst = stream.Endpoint(ax_description(32, 32))
-        ax_beat = stream.Endpoint(ax_description(32, 32))
-        dut =  LiteDRAMAXIBurst2Beat(ax_burst, ax_beat)
-
-        # generate dut input (bursts)
-        prng = random.Random(42)
-        bursts = []
-        for i in range(32):
-            bursts.append(Burst(prng.randrange(2**32), BURST_FIXED, prng.randrange(255), log2_int(32//8)))
-            bursts.append(Burst(prng.randrange(2**32), BURST_INCR, prng.randrange(255), log2_int(32//8)))
-        bursts.append(Burst(4, BURST_WRAP, 4-1, log2_int(2)))
-
-        # generate expexted dut output (beats for reference)
-        beats = []
-        for burst in bursts:
-            beats += burst.to_beats()
-
-        # simulation
-        generators = [
-            bursts_generator(ax_burst, bursts),
-            beats_checker(ax_beat, beats)
-        ]
-        run_simulation(dut, generators)
-        self.assertEqual(self.errors, 0)
-
     def _test_axi2native(self,
         naccesses=16, simultaneous_writes_reads=False,
         # rand_level: 0: min (no random), 100: max.